Elliot Mednick is Lead Architect for Embedded Systems Design at Cadence Design Systems.  He has over 20 years experience in computer hardware and system software development and architecture, as well as ASIC development, verification infrastructure, and simulation tool development. More recently, he has implemented several hardware/software coverification tools, including one for a multiprocessor-based network processor.  Elliot was a voting member of the IEEE 1364-1995 working group, program committee member for HDLCON/IVC and the program chair of HDLCON in 1998, and is currently on the Accellera SCE committee.