Norbert Wehn University of Kaiserslautern, Germany
Norbert holds the chair for Microlectronic System Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern. He has more than 200 publications in various fields of microelectronic system design and holds several patents. He is vice-chair of the European Design Automation Association, Chairman of the Research Center "Ambient Systems" at TU Kaiserslautern, associate editor of various journals and member of several scientific advisory boards. In 2003 he served as program chair for DATE 2003 and as general chair for DATE 2005 respectively. He is IEEE golden core member and DATE fellow. His special research interests are VLSI-architectures for mobile communication, forward error correction techniques, low-power, advanced SoC architectures and reliability issues in SoC.

David Atienza, EPFL, Switzerland
David Atienza received his MSc and PhD degrees in Computer Science from Complutense University of Madrid (UCM), Spain, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. Currently, he is Professor and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland, and Adjunct Professor at the Computer Architecture and Automation Department of UCM. His research interests focus on design methodologies for high-performance embedded systems and Systems-on-Chip (SoC), including new thermal management techniques for Multi-Processor SoCs, dynamic memory management and memory hierarchy optimizations for embedded systems, novel architectures for logic and memories in forthcoming nano-scale electronics and 3D integrated circuits, as well as Networks-on-Chip design. In these fields, he is co-author of more than 100 publications in prestigious journals and international conferences. He is an Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design), IEEE Letters on Embedded Systems and Elsevier Integration: The VLSI Journal. He is also an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008.

Katalin Popovici, MathWorks, France
Dr. Katalin Popovici received her Engineer Degree in Computer Science from University of Oradea, Romania in 2004, and her Ph.D. in Micro and Nano Electronics from Grenoble Institute of Technology, France in 2008. Currently she is working as Senior Software Engineer at The MathWorks, in the Simulink Core development team. Her research interests include system level modeling and design of MPSoC, programming models, and code generation for embedded multimedia applications.

Gerd  Ascheid, RWTH Aachen University, Germany

Soo-Ik Chae, Seoul National University, Korea

Pieter Vander Wolf, NXP, Netherlands
Pieter van der Wolf is a Senior Principal Scientist at NXP Semiconductors Research. He received his MSc and PhD degrees in Electrical Engineering from Delft University of Technology. In 1996 he joined Philips Research. In 2006 he joined NXP Semiconductors when it was spun out of Philips Electronics. His main interests are (multi-)processor architectures and system design methodologies. He currently is heading a research project on SoC infrastructures and is the NXP Technology Competence Manager for the SoC architecture domain.

Gerhard Fettweis,Technical University Dresden, Germany

Kasutoshi Wakabayashi, NEC, Japan

Kees Goossens, NXP, Netherlands
Kees Goossens received his BSc in computer science from the University of Wales in 1988, and his PhD from the University of Edinburgh in 1993. In his thesis he investigated the formal verification of hardware, in particular by using semi-automated proof systems in conjunction with formal semantics of hardware description languages such as ELLA and VHDL. He continued this work at several other universities before joining NXP Semiconductors Research (formerly Philips Research) in the Netherlands in 1995. At NXP he worked on behavioural synthesis for high-throughput video processing, then on on-chip communication protocols and memory management. Since 2000, he has worked on networks on chip for consumer electronics systems, where real-time predictability (QoS) and costs are major constraints. Since 2007 he has also been full professor at the Delft University of Technology.

Chris Rowen, Tensilica, USA
Dr. Chris Rowen Founder, Chief Technology Officer, member of the board of directors, and Tensilica's first president. He was a pioneer in the development of RISC architecture at Stanford in the early 80s and helped start MIPS Computer Systems Inc. in 1984, where he served as Vice President for Microprocessor Development. Most recently, he was Vice President and General Manager of the Design Reuse Group of Synopsys Incorporated. Since 1997 he has focused on developing Tensilica's team, market, business and technology for wide adoption of automatically generated processors and software, especially for dataplane processing in SOCs for communication, consumer and computation systems. He received a B.A. in physics from Harvard University and M.S. and Ph.D. in electrical engineering from Stanford University.

Jenq-Kuen Lee, National Tsing-Hua University, Taiwan

Guy Bois, Ecole Polytechnique Montréal, Canada

Nicolas Darbel, STEricsson, France
Nicolas Darbel graduated and obtained his PhD diploma from ENST, Paris (Ecole Nationale Supérieure des Télécommunications) in 1991. He worked several years as a scientist and an assistant professor at ENST. He joined the industry in 1997 and worked on micro-processor architecture and wireless applications for several companies in San Diego, CA (Metaflow Technology, Dot Wireless, ST). He is the author of a couple of patents in the field of CDMA / WCDMA. Nicolas Darbel is currently design manager for U8500 top level integration at ST-Ericsson, Grenoble in the organization of Abdellah Er Rachidi.

Koichiro Yamashita, Fusitu Labs, Japan

Thierry Collette, CEA LIST, France
Dr. Thierry Collette is in charge, at CEA LIST, of the embedded computing activities. Since 2004, he leads the Architecture and Design Department. This unit is comprise of 100 researchers and its work focuses on embedded computing, embedded Operating System, embedded reliability, tools for many-core architectures and embedded computer vision. Before this, Thierry Collette was the head of the embedded computer laboratory of LETI and designed several parallel and reconfigurable embedded computers. He obtained an Electrical Engineering Degree in 1988 and a Ph.D in Microelectronics of the University of Grenoble in 1992. He wrote, as author and co-author, several papers for conferences and journals on embedded parallel and reconfigurable computing and is also the holder of several patents. He teaches computer architecture for master's degree program at Ecole Centrale of Paris and University of Paris XI. He is CEA senior expert in embedded computing and has evaluated several international and national projects (MEDEA, ANR, OSEO, etc). He is co-chair of specific program in the evaluation committee of the French National Research Agency.

Lars Bauer , University of Karlsruhe, Germany
Lars Bauer received his Diploma Degree in Computer Sciences from the University of Karlsruhe, Germany in 2004. His main research interests are extensible processors and reconfigurable computing systems with a focus on dynamically varying run-time situations and concepts that allow systems to adapt to changing requirements. He is currently working at the Chair for Embedded Systems (CES), University of Karlsruhe. Recently, he received the DATE'08 best paper award and a HiPEAC paper award (for DAC'08 paper) for his work on adaptive reconfigurable processors.

Gabriela Nicolescu, Ecole Polytechnique de Montréal, Canada

Joachim Kunkel, Synopsys, USA

Koji Inoue, Kyushu University, Japan
Koji Inoue was born in Fukuoka, Japan in 1971. He received the B.E. and M.E. degrees in computer science from Kyushu Institute of Technology, Japan in 1994 and 1996, respectively. He received the Ph.D. degree in Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University, Japan in 2001. He is currently an associate professor of the Department of Advanced Information Technology, Kyushu University. His research interests low-power cache architectures, power-aware computing, high-performance computing, and secure computing.

Hyunchul Shin, Hanyang University, Korea
Hyunchul Shin received the B.S. degree in Electronics Engineering from Seoul National University, and the M.S. degree in Electrical Engineering from the Korea Advanced Institute of Science and Technology in 1978 and 1980, respectively. He received a Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California at Berkeley in 1987. From 1980 to 1983, he was with the Department of Electronics Engineering at the Kum-Oh Institute of Technology, Korea. In 1983, he received a Fullbright scholarship. From 1987 to 1989, he was a member of the technical staff at AT&T Bell Laboratories, Murray Hill, NJ. Since 1989, he has been a professor in the School of Electrical and Computer Engineering at Hanyang University, Korea. He is the president of the Multi-core Design Methodology (MDM) Research center. His research interests include the design and synthesis of integrated circuits and system.

Wen-mei Hwu, Illinois University, USA
Wen-mei W. Hwu is a Professor and holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. His research interests are in the area of architecture, implementation, and software for high performance computer systems. He is the director of the IMPACT research group (www.crhc.uiuc.edu/Impact). For his contributions in research and teaching, he received the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and ISCA Most Influential Paper Award. He is a fellow of IEEE and ACM. Hwu serves on the Executive Committee of the MARCO/DARPA C2S2 (www.c2s2.org) and GSRC (www.gigascale.org) Focus Research Centers. He leads the GSRC Concurrent Systems Theme. He co-directs the new $18M UIUC Intel/Microsoft Universal Parallel Computing Research Center with Marc Snir and serves as one of the principal investigators of the $208M NSF Blue Waters Petascale computer project. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.

Tsuyoshi Isshiki, Tokyo Institute of Technology, Japan
Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently an Associate Professor at Tokyo Institute of Technology, Dept. of Communications and Integrated Systems. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.

Nishii Osamu, Renesas Technology, Japan
Osamu Nishii received the B.S. and M.S. degrees in mathematical engineering and instrumentation physics from the University of Tokyo, Japan, 1985 and 1987, respectively. In 1987 he joined Hitachi, Ltd. In 2004, he moved to Renesas Technology Corporation where he has been engaged in and development of SuperH processors. His current interest is processor architecture and logic design.

Reiner Hartenstein , TU Kaiserslautern, Germany
Reiner Hartenstein is CS professor at TU Kaiserslautern and was visiting professor at UC Berkeley. All his degrees are from Karlsruhe Institute of Technology. He is consultant and authorized expert and referee on Information Technology. In research he is credited to be the father of Reconfigurable Computing. He is author of the hardware language KARL, trailblazer for VHDL and Verilog. He is founder of three, and co-founder of two more successful international conference series, as well as founder of the Multi University VLSI Design Project „E.I.S.“, the German contribution to the Mead-&-Conway VLSI design revolution. He is IEEE life fellow, SDPS fellow, FPL fellow, and recipient of several other awards He has published 14 books and more than 400 technical papers and has given numerous talks, including more than 200 invited talks and more than 20 keynote addresses.

Alain Greiner, LIP6-ASIM, France
Alain GREINER was born in Paris in 1952. He got his PHD from University Denis Diderot (Paris 7) in 1982, after working six years at "Commissariat à l'Energie Atomique" as a research engineer in nuclear physics. From 1982 to 1986 he was assistant professor in VLSI design at University Pierre et Marie Curie (Paris 6). He joined the BULL company in 1996, as a senior engineer. He was project leader for the VLSI design of the Basic Processing Unit of the DPS7000 computer, the most powerfull mainframe in this family. Since 1990, Alain GREINER has a permanent position as a professor at University Pierre et Marie Curie. He was director of the MASI Laboratory from 1994 to 1997, and is presently director of the SoC department of LIP6. He was the project leader for the ALLIANCE CAD system. This public domain VLSI CAD system is distributed and used in more than 250 universities worlwide. He is now leading the SoCLib project,, that is an open virtual prototyping platform for MPSoC design. Alain Greiner is a co-founder of two start-up companies : Thachys Technologies was created in 1996 in order to make commercial exploitation of the HSL serial link technology . Avertec was created in 1998 in order to make commercial exploitation of several VLSI/CAD tools for verification of deep-submicronic design.

Pierre Paulin, STMicroelectronics, Canada
Dr. Pierre Paulin is director of System-on-Chip Platform Automation at STMicroelectronics, Ottawa, Canada. Previously, he was director of Embedded Systems Technologies for ST in Grenoble, France. Before this, he managed embedded software tools and high-level synthesis R&D with Nortel Networks research labs. He obtained a Ph.D. from Carleton University, Ottawa, in 1988, and B.Sc. and M.Sc. degrees from Laval University, Quebec in 1982 and 1984 respectively.

Olivier Franza, Intel, USA
Olivier Franza is an Intel senior staff technical leader in the Digital Enterprise Group, in the area of clock generation and distribution architecture and design since 2005. He is involved in various ItaniumT and high-end XeonT projects and previously participated in the design of the Intel IXP28xx network processor family and the Intel Nehalem-EX XeonT microprocessor family. Olivier joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel. Prior to joining Intel, Olivier held senior hardware engineer positions during 3 years of combined service at Compaq and Digital Equipment Corporation on both the Alpha 21364 (EV7) and 21464 (EV8) microprocessors since 1998. Olivier received both his electrical engineering degree from Supélec, France, and his master of science degree from the University of Illinois at Urbana-Champaign, USA, in 1994. He earned both his doctorat en sciences degree from Paris XI University, France, and his doctorate degree from the University of Illinois at Urbana-Champaign, USA, in 1998. Olivier is the coauthors of more than 20 conference papers and publications; he is the general co-chair of MPSoC 2009, the multi-processor system-on-a-chip conference.

Charlie Janac, Arteris, USA

Ahmed Jerraya, CEA-LETI, MINATEC, France
Dr. Ahmed Jerraya is Director of Strategic Design Programs at CEA/LETI France. He served as General Chair for the Conference DATE in 2001, Co-founded MPSoC Forum (Multiprocessor system on chip) and is the organization chair of ESWEEK2009. He supervised 51 PhD, co-authored 8 Books and published more than 250 papers in International Conferences and Journals.

Drew Wingard, Sonics, USA

Srinivasan Muralli, Inocs, Switzerland
Srinivasan Murali is a co-founder and CTO of iNoCs. He also holds a research scientist position at EPFL. He received the MS and PhD degrees in Electrical Engineering from Stanford University in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chips. His interests also include thermal modeling and reliability of multi-core systems. He is a recipient of the EDAA outstanding dissertation award for 2007 for his work on interconnect architecture design. He received a best paper award at the DATE 2005 conference and a best paper nomination at the ICCAD 2006 conference. One of his papers from the DATE 2004 conference has also been selected as one of "The Most Influential Papers of 10 Years DATE". He has authored a book, and holds several patents and over 30 publications in leading conferences and journals in this field. He has been actively involved in several conferences (such as DATE, CODES-ISSS, NoC symposium, VLSI-SoC, MPSoC) as a program committee member/session chair and is a reviewer for many leading conferences and journals.

John Goodacre, ARM, UK
John joined ARM in February 2002 and took responsibility for their platform architecture. Today he has responsibility for the application processor's technology roadmap including the definition and market development of the ARM MPCore multicore processor technology now realized in both the ARM11 MPCore and the Cortex-A9 MPCore.
Prior to working at ARM, he specialized in enterprise software having worked for Microsoft for 5 years, firstly as Group Program Manager in the Exchange Server group and latterly as the manager of a team developing mobile phones software.
Graduating from the University of York with a BSc in Computer Science, John has over 20 years experience of realizing new technologies in the engineering industry.

Scott Mahlke, Michigan University, USA
Scott Mahlke is an Associate Professor in the EECS Department at the University of Michigan where he directs the Compilers Creating Custom Processors research group. The CCCP group delivers technologies in areas of domain-specific processors and accelerators, compiler technology, and low-power computing. Mahlke received the PhD University of Illinois in 1997 and spent 6 years as a research scientist at Hewlett-Packard Laboratories.

Tom Conte, Georgia Institute of Technology, USA

Chris Rowen, Tensilica, USA

Sanjay Patel, Illinois University, USA
Sanjay J. Patel is an Associate Professor of Electrical and Computer Engineering and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign. He has done architecture, hardware verification, logic design, and performance modeling at Digital Equipment Corporation, Intel Corporation, and HAL Computer Systems, as well as provided consultation for Transmeta, Jet Propulsion Laboratory, HAL, Intel, and AGEIA Technologies. From 2004 through 2008, he served as the Chief Architect and Chief Technology Officer at AGEIA Technologies, prior to its acquisition by Nvidia Corp. Patel earned his Bachelor (1990), Master of Science (1992) and Ph.D. (1999) in Computer Science and Engineering from the University of Michigan, Ann Arbor. He is the co-author (with Yale N. Patt of The University of Texas at Austin) of an introductory textbook for computer science and engineering students, titled "Introduction to Computing Systems: From Bits and Gates to C and Beyond", which is now available in its second edition from McGraw-Hill.

Tohru Ishihara, Kyushu University, Japan

Hiroyuki  Tomiyama, Nagoya University, Japan
Hiroyuki Tomiyama received his Ph.D. degree in computer science from Kyushu University in 1999. From 1999 to 2001, he was a visiting postdoctoral researcher with the Center of Embedded Computer Systems, University of California, Irvine. From 2001 to 2003, he was a researcher at the Institute of Systems & Information Technologies/KYUSHU. In the meantime, he was also a visiting associate professor at Kyushu University and a researcher at Semiconductor Technology Academic Research Center (STARC). In 2003, he joined the Graduate School of Information Science, Nagoya University, as an assistant professor, where he is now an associate professor. His research interests include design automation, architectures and compilers for embedded systems and systems-on-chip.

Fredrik Dahlgren, ST-Ericsson
Fredrik Dahlgren is head of Technology Roadmap and Strategy at the Mobile Platforms product group of ST-Ericsson. He received an M.Sc. and Ph.D. in Computer Engineering at Lund University in 1990 and 1994, respectively. After being a visiting scientist at M.I.T. during 1995/96, he became an assistant professor at Chalmers University of Technology 1996. He has been with Ericsson Mobile Platforms from 1999 to the creation of ST-Ericsson joint-venture 2009 in various different roles, including head of the Research Department as well as senior roles in Product Management, System Architecture, and Technology Strategy. In addition to his contributions within Ericsson and ST-Ericsson, Dr. Dahlgren has published some 35 scientific papers in well-regarded journals and conferences, and he has served on the program committee of several international conferences as well as expert committees of research funding evaluations.

Sarath Sriprakash, Northrup Grumman, USA
Dr. Sarathy has been active in the area of Advanced Flight Software through his position as Manager, Technology Development for the UCAS program at Northrop Grumman Corp. He is also the PI for the AFRL sponsored Mixed Criticality Architecture Program (MCAR), which seeks to redefine the certification, verification, validation and testing of advanced flight software in the context of mixed critical systems. His background spans both software systems as well as Aerospace Engineering, and thus provides a strong context to his views on hardware drivers to support emerging complex flight software capabilities onboard future unmanned systems.

Jan Madsen, Technical University of Denmark, Denmark

Sungjoo Yoo, Postech , Korea
Dr. Sungjoo Yoo received B.S., M.S., and Ph.D. at Seoul National University, Korea, in 1992, 1995, and 2000, respectively. He worked at TIMA laboratory, Grenoble, France from 2000 to 2004. He worked for System LSI Division, Samsung Electronics from 2004 to 2008. He joined POSTECH (Pohang university of science and technology) in August 2008. His current research interests include many-core architecture for multiple memories, NAND Flash-based solid state disk, and DVFS-based low power design methods

Kiyoung Choi, Seoul National University, Korea
Kiyoung Choi is a professor of the Department of Electrical Engineering and Computer Science, Seoul National University. He received B.S. degree in electronics engineering from Seoul National University in 1978 and M.S. degree in electrical and electronics engineering from KAIST in 1980. He received Ph.D. degree in electrical engineering from Stanford University in 1989. He worked for Cadence Design Systems from 1989 to 1991. His research interests are in computer architecture, embedded systems design, low power design, and design automation.

Vijaykrishnan Narayanan, Pennsylvania State University, USA
Vijaykrishnan Narayanan is a Professor of Computer Science and Engineering at The Pennsylvania State University. His research interests are Computer Architecture, Nanoarchitectures and Embedded Systems.

Suzane Lesecq, INPG, France

Yuan Xie, Pennsylvania State University, USA
Yuan Xie is Associate Professor in Computer Science and Engineering department at the Pennsylvania State University. He received Ph.D. degree in electrical engineering from Princeton University. He was a recipient of NSF CAREER award in 2006, and IBM Faculty Award in 2008. He also received Best Paper Award in ASP-DAC 2008. He is a co-editor for a new book titled "3D ICs: Design, CAD, and Architecture", which will be published by Springer in Sept. 2009.

Takeuchi Yoshinori, Osaka University, Japan
He received his B.E., M.E. and Dr. Eng. degrees from Tokyo Institute of Technology in 1987, 1989 and 1992, respectively. From 1992 through 1996, he was a research associate of Department of Engineering, Tokyo University of Agriculture and Technology. From 1996, he has been with the Osaka University. He was a visiting scholar in University of California, Irvine from 2006 to 2007. He is currently an Associate Professor of Graduate School of Information Science and Technology at Osaka University. His research interests include System Level Design, VLSI design and VLSI CAD. He is a member of IEICE of Japan, IPSJ, ACM, and SP, CAS and SSC Society of IEEE.

Matthew Mattina, Tilera, USA
Matthew Mattina is a principal engineer at Tilera Corporation and the lead architect of the TILEPro multicore processor family. Prior to joining Tilera in 2005, he was a CPU architect at Intel and Digital Equipment Corporation. He holds several patents relating to processor architecture and design. Mattina received the BS in Computer Engineering from Rensselaer Polytechnic Institute in 1995 and the MS in Electrical Engineering from Princeton University in 1997. He is a member of the IEEE.

Janos Sztipanovits, Vanderbilt University, USA

Omar Hammami, ENSTA, France
Omar Hammami is with ENSTA/DGA. He has been involved on several research projects for embedded systems both for civilan and military involving SOC and MPSOC design. Prior to that he was an Associate Professor in the University fo Aizu, Japan and Head of the Performance Evaluation Laboratory. His research interests are MPSOC design, EDA and SCA-JTRS compliant Cognitive Radio.

Ulrich Ramacher, Infineon,

Rolf Ernst, Technical University of Braunschweig, Germany
Rolf Ernst received a diploma in CS and a Dr.-Ing. in EE from the University of Erlangen-Nuremberg, Germany, in 81 and 87. From 88 to 89, he was with Bell Laboratories, Allentown, PA. Since 90, he has been a professor of electrical engineering at the Technische Universität Braunschweig, Germany, where he chairs a university institute of 60 researchers and staff. He was Head of the Department of Electrical Engineering from 1999 to 2001.
His research activities include embedded system design and design automation. The activities are currently supported by the German "Deutsche Forschungsgemeinschaft" (corresponds to the NSF), by the German BMBF, by the European Union, and by industrial contracts, such as from Intel, Thomson, EADS, Ford, Bosch, and Volkswagen. He gave numerous invited presentations and tutorials at major international events and contributed to seminars and summer schools in the areas of hardware/software co-design, embedded system architectures, and system modeling and verification.
He is an IEEE Fellow and served as an ACM-SIGDA Distinguished Lecturer. He is a member of the German Academy of Science and Engineering, acatech.

Frédéric Pétrot, TIMA-SLS, France
Frédéric Pétrot received the PhD degree in Computer Science from Université Pierre et Marie Curie (Paris VI), Paris, France, in 1994, where has been Assistant Professor in Computer Science until September 2004. From 1989 to 1996, he was one of the main contributors of the open source Alliance VLSI CAD system that received the Seymour Cray award in 1994 (www-asim.lip6.fr/recherche/alliance). Since 1996, he headed the work on the definition and implementation of the Disydent system-level design environment at UPMC, oriented toward the specification and implementation of multiprocessor SoCs (www-asim.lip6.fr/recherche/disydent). Since September 2004, he is a Professor at the Institut Polytechique de Grenoble, France, where he leads (since 2006) the System Level Synthesis Group of the TIMA Lab. His research interests range from CAD for circuit and system to multiprocessor architectures.

Marcello Coppola, STMicroelectronics, France
Marcello Coppola received the Master degree in Computer Science from Pisa University, in 1992. Previously, he was with the Transputer architecture group at INMOS (UK) working on the architecture of the C104 router. He is now an R&D Director of STMicroelectronics. He introduced the NoC in ST and he is responsible of Spidergon STNoC program; managing architecture, design, prototyping and modeling teams. Moreover, he is coordinating several world-wide university and European research programs. His research interests include design methodologies for system-on-chip, with particular emphasis to network-on-chip, multicore and many-core architectures, parallel programming and system level design.  He has published several research articles in various books and journals. He was a member of the OSCI language working group contributing towards SystemC2.0 definition and OSCI standardization. He was an early introduced of SystemC in ST. He has been chair of many international conferences on SoC design and has helped in organizing several others. He has been a program committee member of DATE, FDL, CODES+ISSS and DAC and has contributed to the MEDEA+ EDA and CATRENE EDA Roadmaps. He is joint inventor on 18 international patents and he is member of the EDAA (European Design Automation Association)