Speaker:

Samar Abdi, Concordia University, Canada

Title:

Hybrid Prototyping of MPSoCs

Abstract:

Pre-silicon performance validation of MPSoCs is a serious challenge. Conventional technologies such as virtual prototyping and physical prototyping have several limitations. Virtual prototypes, based on host-compiled instruction-set simulators, can provide high simulation speed, but at the expense of limited or no timing accuracy. Physical prototypes, based on instantiation and integration of processor cores in FPGA, provide cycle accuracy, but with the disadvantage of high development cost and lack of scalability. In addition, there is no flexibility of abstracting the inter-core communication in physical prototypes, since it is fixed in hardware. Furthermore, software debugging on multiple processors in FPGA can be quite challenging. In this talk, I will present a novel modeling technique for MPSoCs, called Hybrid Prototyping. The fundamental idea is to simulate a design with multiple processor cores by creating an emulation kernel in software on top of a single physical instance of the processor in FPGA. The emulation kernel switches between tasks mapped to different cores and manages the logical simulation times of the individual processor cores. As a result, we can achieve fast and cycle-accurate simulation of MPSoCs, thereby overcoming the accuracy concerns of virtual prototyping and the scalability issues of physical prototyping. Our experiments with industrial MPSoC designs show that the simulation time with hybrid prototypes grows only linearly with the number of cores and the inter-core communication traffic, while providing cycle accuracy.

Bio:

Samar Abdi is an Assistant Professor of Electrical and Computer Engineering at Concordia University, Montreal, Canada since August 2009. He received his PhD in Computer Science from University of California, Irvine (UCI) in 2005 and B.Tech. in Computer Science and Engineering from IIT Kharagpur in 1998. From 2006 to 2009, he was an Assistant Project Scientist at UCI, leading a project on Embedded System Modeling as part of the Giga-Scale Systems Research Center. From 1998 to 2000, he was a member of technical staff at Cadence Design Systems, working on logic simulation tools. He is the architect and development lead of Embedded System Environment (ESE), a framework for modeling, synthesis and verification of MPSoC-based embedded systems. He has authored a book on Embedded System Design and over 30 peer-reviewed conference and journal papers.