Speaker:

Marcello Coppola, STMicroelectronics, France

Title:

Virtualization-ready SoC: challenges for heterogeneous multi-core architectures

Abstract:

Nowadays consumer and mobile devices are pervasive in our everyday live and the application complexity is increasing exponentially. System-on-Chips for such devices are heterogeneous multi-core processors with specific hardware accelerators in which the performance/watt ratio is key selling and differentiation point. The required SoC flexibility is promoting an application-centric model, which faces new challenges such as openness (total decoupling from hardware to application software), security, programmability and performance. Virtualization, widely used in modern datacenter, allowing server consolidation, energy efficiency, green IT, business continuity, disaster recovery and data protection, could be also suitable to cope with some of the challenges faced by heterogeneous multi-core embedded systems. In this presentation, first a virtualization-ready SoC architecture addressing the aforementioned challenges will be presented. Next, we introduce the hardware virtualization by focusing not only on the well-known processor virtualization but on the hardware assisted virtualization for the overall SoC. Finally, some real scenarios in which virtualization could bring an added value are presented.

Bio:

Marcello Coppola graduated in Computer Science from the University of Pisa, Italy in 1992. He joined the Transputer architecture group in INMOS, Bristol (UK), doing research in multi-core communication together with the key technical people of Transputer technology with special focus in the C104 router. Later, he moved to the Advanced System Technology R & D group of STMicroelectronics, in which started and leaded different research programs. The last one, he and his team developed the first industrial multiple-die Network-on-Chip called Spidergon STNoC, ended with the deployment company-wide of the technology and first integration in different 32nm multimedia and mobile SoCs. Currently, he is advanced architecture & innovation Director within the digital sector group, of STMicroelectronics, in Grenoble (France). Technology innovator with the ability to accurately predict technology trends, problem emergence and solution requirements. In charge of advanced research and collaborative project proposals inside different funding schemes. His research interests include several aspects of design technologies for Multicore, Manycore System-on-Chip including server, with particular emphasis to architecture, modeling, verification, network-on-chip and programming models. He's co-author and/or co-editor of different books and of over 50 technical articles. He is serving or has served as program and/or organizing member in numerous top international conferences and workshops. He has also served as reviewer for international conferences as well as journals and holds a number of patents.