Speaker:

Hiroshi Nakamura, The University of Tokyo, Japan

Title:

Challenges and Opportunities of Normally-Off Computing

Abstract:

It is indispensable for our modern society to reduce power consumption of computer systems. "Normally-Off" is believed as one of the most promising ways to achieve this goal, which aggressively powers off components of computer systems when they need not to operate. This idea is based on the observation that all the components need not always work during computation. However, chances for power reduction cannot not be fully utilized because volatile memories such as SRAM, and DRAM lose data when power is turned off. Recently, new memory devices, called Non-Volatile Memory (NVM), including MRAM, FeRAM, and PRAM, have appeared, and hence, high attention has been paid to Normally-Off Computing using these NVMs. However, because NVMs consume larger energy and take longer time than volatile memories when accessed, power is not always reduced by simply replacing volatile memories with NVMs. In this talk, challenges and opportunities of Normally-Off Computing are addressed with brief introduction of the NEDO project started in 2011.

Bio:

Hiroshi Nakamura is a Professor at the Department of Information Physics and Computing in the Graduate School of Information Science and Technology at The University of Tokyo. He received the Ph.D. degree in Electrical Engineering from The University of Tokyo in 1990. His research interests include power-efficient computer architecture and VLSI design for high-performance and embedded systems. He led the project of "Innovative Power Control for Ultra Low-Power and High-Performance System LSIs" supported by JST (Japan Science and Technology Agency) from 2007 to 2012, and is now leading the "Normally-Off Computing Project" supported by NEDO/METI. He served IEEE ISLPED 2011 as a general chair. He is a senior member of IEEE and ACM.