Speaker:

Tsuyoshi Isshiki, Tokyo Institute of Technology, Japan

Title:

Trace-Driven MPSoC Simulation with Cache Modeling

Abstract:

This talk focuses on the MPSoC architecture evaluation framework for estimating the performance of MPSoC applications with emphasis on bus traffic simulation with cache models. Our trace-driven workload model automatically generated from the application code accurately reflect the timing behavior of each processors, while cache statistics at each memory access are collected offline during native code execution which is used to generate bus traffic induced by cache misses. A variety of bus architectures with multiple memories, processors, caches and DMACs can be simulated with near cycle accuracy with comparable speed of native SW execution.

Bio:

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently an Associate Professor at Tokyo Institute of Technology, Dept. of Communications and Integrated Systems. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.