Speaker:

K. Charles Janac, Arteris Inc., USA

Title:

Interconnect Observability for Software Productivity

Abstract:

In highly distributed SoCs with hundred IPs and distributed multi-core processors, the only IP in the SoC that sees the entire data traffic picture is the Network on Chip(NoC) interconnect. This presentation covers the role of a dedicated observability Network on Chip that allows statistical tracking of data for post-silicon debug and performance optimization. The presentation also explores the potential for completing an observability feedback system between SoC-level analytics and system-level software to enhance overall system performance.

Bio:

K. Charles Janac is the Chairman, President and Chief Executive Officer of Arteris Holdings and its subsidiaries. Arteris has pioneered the market for Network on Chip (NoC) interconnect IP and Tools for on-chip communications in System on Chip (SoC) type semiconductors. Arteris products are designed into some of the highest volume SoCs being delivered today by companies such as Qualcomm, Samsung and Texas Instruments. Charlie has nearly 30 years of experience building technology companies. He started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a publicly traded software company. Subsequently, he served as President/CEO of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California. Born in Prague, Czech Republic, he holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business. Charlie, his wife Lydia, and their two sons reside in Los Altos Hills, California.