13th International Forum on Embedded MPSoC and Multicore
July 15-19, 2013, Otsu, Japan
Speaker:
Hiroyuki Tomiyama, Ritsumeikan University, Japan
Title:
Simulation of Many-core NoCs with QEMU and SystemC
Abstract:
This talk describes a fast and regargetable simulator of many-core NoCs. Each core is emulated by a QEMU, and the network part including NoC routers is modeled with SystemC. The SystemC simulator and QEMUs are connected by TCP sockets on a host computer. Our simulator is fast because QEMUs run in parallel on a multi-core host computer or even multiple host computers. Also, our simulator is highly retargetable because QEMU provides a variety of CPU models and we use QEMU as is. In our experiments, our simulator successfully simulates a 108-core NoC in a practical time.
Bio:
Hiroyuki Tomiyama received his Ph.D. degree in computer science from Kyushu University in 1999. From 1999 to 2001, he was a visiting postdoctoral researcher with the Center of Embedded Computer Systems, University of California, Irvine. Then, he worked for Institute of Systems & Information Technologies/KYUSHU as a researcher and Nagoya University as an associate professor. In 2010, he moved to Ritsumeikan University as a full professor. His research interests include system-level design methodology for embedded systems and MPSoC. He is General Co-Chair of MPSoC 2013, Editor-in-Chief of IPSJ Transactions on System LSI Design Methodology, and Chair of IEEE Computer Society Kansai Section.