14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Chris Rowen, Cadence, USA
Making High Performance Vision Processing Real
In this talk we discuss both the essential computational demands for embedded video rate vision processing and show off the capabilities of a new vision-oriented DSP processor subsystem of the IVP family, including both core architecture and software environment. The talk highlights novel processing methods to uncover and exploit parallelism at multiple levels in vision-centric algorithms.
Dr. Chris Rowen is a Cadence Fellow He joined Cadence after the acquisition of Tensilica, the company he founded in July 1997. Initially, he was president and CEO of Tensilica; more recently he was Chief Technology Officer, instrumental in the design architectures for Tensilica's baseband and imaging products. He was a pioneer in the development of RISC architecture at Stanford in the early 80s and helped start MIPS Computer Systems Inc. in 1984, where he served in a variety of functions including as Vice President for Microprocessor Development. When Silicon Graphics purchased MIPS, he became the technology and market development leader for Silicon Graphics Europe. In 1996, he became Synopsys' Vice President and General Manager of the Design Reuse Group. He received a B.A. in physics from Harvard University and M.S. and Ph.D. in electrical engineering from Stanford University.
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