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Dr. Fumio Arakawa, Nagoya University, Japan


Nanoprocessor Cluster: Conversion from ILP to uTLP


Now a multi-many-core processor is one of the most popular way to achieve high-performance. In order to realize the potential performance of the multi-many cores, we must extract task or thread level parallelism (TLP) by dividing a program into multiple threads loosely coupled each other. Tightly coupled operations must be in a single thread to avoid the overhead for synchronizations and data transfers. The thread of tightly coupled operations can be parallelized by extracting instruction level parallelism (ILP). However, the ILP extraction is inefficient for long latency operations. I will introduce a "Nanoprocessor Cluster" to convert the ILP to micro-thread level parallelism (uTLP) for the efficient parallelization of such a program with tightly-coupled long-latency operations.


Fumio Arakawa is a designated professor of Graduate School of Information Science at Nagoya University. His research interests include architecture and micro-architecture of low-power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He's a program committee co-chair of the Cool Chips conference series, a program committee member of the VLSI Circuits Symposium, a steering committee member of International Symposium on Embedded Multi/Many-core SoCs, and the chairman of Microprocessor Technical Committee of Japan Electronics and Information Technology Industries Association. He's a member of IEEE and the Institute of Electronics, Information, and Communication Engineers.

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