Prof. Gerhard P. Fettweis, TU Dresden, Germany


The TOMAHAWK-2: A Runtime Adaptive MPSoC


Next generation wireless terminal as well as base station silicon systems need to be addressing a wide range of challenges: scalability in processing power, scalability in power consumption, extreme low-power modes, flexibility in addressing the different processing kernels, and the ability to address all parameters at runtime to modify the execution mode as boundary conditions change. We have come up with an MPSoC concept, within which addresses all main point. We can adapt processor cores, frequency, voltage, as well as availability of resources. This is carried out without disrupting the computation, as a fully flexible run-time novel hierarchical core-manager caries out the space/time control of the system setup as well as the scheduling of all software tasks. This concept was implemented in the TOMAHAWK-2 chip, fabricated in 65nm CMOS. The real-time lab tests show the full functionality of the concept, outperforming alternative MPSoC platforms with clear margin.


Gerhard Fettweis earned his Ph.D. under H. Meyr's supervision from RWTH Aachen in 1990. After one year at IBM Research in San Jose, CA, he moved to TCSI Inc., Berkeley, CA. Since 1994 he is Vodafone Chair Professor at TU Dresden, Germany, with currently 20 companies from Asia/Europe/US sponsoring his research on wireless transmission and chip design. He coordinates 2 DFG centers at TU Dresden, namely cfAED and HAEC.
Gerhard is IEEE Fellow, member of acatech, has an honorary doctorate from TU Tampere, and has received multiple awards. In Dresden he has spun-out eleven start-ups, and setup funded projects in volume of close to EUR 1/2 billion. He has helped organizing IEEE conferences, most notably as TPC Chair of ICC 2009 and of TTM 2012, and as General Chair of VTC Spring 2013 and DATE 2014.

* If you wish to modify any information or update your photo, please contact the web chairmpsoc2014@imag.fr