14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Dr. Giovanni Beltrame, École Polytechnique de Montréal, Canada
Efficient Device Lifetime Estimation via Design Space Pruning
System-level design space exploration (DSE) is an important process to optimize complex multi-processor system-on-chip (MPSoC) architectures. During DSE, a system's configuration can be modified to improve, among other metrics, the system's expected lifetime, usually based on the estimation of the Mean-Time-To-Failure (MTTF) of the system. Typically, the simulation time to evaluate the MTTF of design points represents a bottleneck for the whole DSE process. Therefore, the vast design space that needs to be searched requires effective design space pruning techniques. We present present a set of metrics to identify similarities among architecture, mapping and wear of a set of configurations, in order to reduce the number of MTTF evaluations needed during system-level DSE.
Giovanni Beltrame received the M.Sc. degree in electrical engineering and computer science from the University of Illinois, Chicago, in 2001, the Laurea degree in computer engineering from the Politecnico di Milano, Italy, in 2002, the M.S. degree in information technology from CEFRIEL, Milan, in 2002, and the Ph.D. degree in computer engineering from the Politecnico di Milano, in 2006. After his PhD he worked as an engineer at the European Space Agency on a number of projects spanning from radiation-tolerant systems to computer-aided design. In 2010 he moved to Montreal, Canada where he is currently Assistant Professor in the Computer Engineering Department at Polytechnique Montreal. His research interests include modeling and design of embedded systems, artificial intelligence, and robotics.
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