14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Prof. James C. Hoe, Carnegie Mellon University, USA
Making Reusable Hardware Design IPs Usable: an NoC perspective
Reusable hardware design IPs have become increasingly parameterizable and even taken on the form of fully on-demand generators. The flexibility of user customization is key to achieving performance and energy efficiency by tailoring the IP instantiations to fit the specifics of the application. At the same time, unfortunately, the complexity and flexibility of IPs have reached a level where the task of understanding and tuning the myriad of parameters can become itself unmanageable for the IP users. This talk argues for a new paradigm for generator-based IPs that encapsulates the IP authors' knowledge to assist the users' interactions with the IP. An IP should not only capture the microarchitectural and structural view of a design, but it should also include (1) characterization meta-data; (2) high-level tuning knobs that are tailored to the specific domain and meaningful to the IP user; (3) domain-aware simulation-time and runtime monitoring and introspection mechanisms; (4) auxiliary supporting material and tools that enhance how the user interacts with the IP. In doing so, the effort that would otherwise be repeated by each IP user is now performed only once by the IP author. To demonstrate the potential of this new IP paradigm we present a case study of extending the CONNECT Network-on-Chip IP generator (http://users.ece.cmu.edu/~mpapamic/connect/) to embody the above principles. This work is the subject of Michael Papamichael's on-going PhD thesis work at Carnegie Mellon University.
James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University. He received his Ph.D. in EECS from Massachusetts Institute of Technology in 2000 (S.M., 1994). He received his B.S. in EECS from UC Berkeley in 1992. He is interested in many aspects of computer architecture and digital hardware design, including the specific areas of FPGA architecture for computing; digital signal processing hardware; and high-level hardware design and synthesis. He co-directs the Computer Architecture Lab at Carnegie Mellon (CALCM) and is affiliated with the Center for Silicon System Implementation (CSSI). He is a Fellow of IEEE. For more information, please visit http://www.ece.cmu.edu/~jhoe.
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