14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Dr. Jos van Eijndhoven, Vector Fabrics, The Netherlands
Programmability of shared-memory multi-core architectures
The proliferation of multi-core architectures is driven by silicon technology scaling rules. However, software application creation is lagging behind to adopt these architectures. The push for energy efficiency leads to ever more complex architectures, with heterogeneous processing and scattered memory blocks, for which programming has become a nightmare. Creating applications on these modern architectures requires a new class of tools to maintain a reasonable programmer productivity. Especially for embedded platforms, silicon vendors typically limit themselves to provide just the basics with a C(++) compiler, linker, debugger, and some low-level run-time libraries. However, to enable development and porting of concurrent applications, higher-level tools are required, that a) help to reveal potential parallelism in the application, and b) verify the correctness of a parallel implementation. In both these domains, tools with appropriate capabilities are very scarce, which hinders the adoption rate of novel architectures. Verifying software correctness in general is too hard, but specifically in the domain of detecting race conditions good progress has been made. Development of such tooling is fueled by the specification of memory ordering behavior of C(++), which only appeared in its recent C++11 standard. This standard specifies constraints and freedom on load/store reordering both in the compiler as well as in the hardware of processors and memory interconnect. With the rules finally being set, novel tooling can indeed successfully flag race conditions. Such progress is important since race conditions in software are a known cause of failures of products in the field and highly expensive product recalls.
Jos van Eijndhoven is CTO and co-founder of Vector Fabrics BV, a company that creates and markets tools for mapping of applications to multi-core architectures. Earlier, he was principal architect at Philips/NXP Research, involved in media-processor architecture and their application programming. Jos received a PhD from the Eindhoven University of Technology, The Netherlands. He holds 15 worldwide patents and is (co)author of about 100 scientific publications.
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