14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
K. Charles Janac, Arteris Inc., USA
Advances in Safety and Resilience in SoC Interconnect
With Network on Chip (NoC) interconnect being used in nearly 200 SoCs, this presentation covers how this technology can be leveraged for mission critical systems, such as automotive or industrial applications. The focus is to describe how safety and resiliency mechanisms in the NoC can become key enablers in meeting various safety goals described in the ISO26262 standard for automotive systems. Solutions presented will include various Error Detection mechanisms, including the, use of Redundant Logic, reliable fault reporting, and generalized use of ECC to assure safe SoC operation. The presentation will speculate that the use of interconnect IP safety and resiliency features may become mainstream for a variety of applications at geometries of 16nm and below.
K. Charles Janac is the Chairman, President and Chief Executive Officer of Arteris Inc.. Arteris has pioneered the market for Network on Chip (NoC) interconnect IP and Tools for on-chip communications in System on Chip (SoC) type semiconductors. Arteris products are designed into some of the highest volume SoCs being delivered today by companies such as Qualcomm, Samsung and Texas Instruments. Charlie has nearly 30 years of experience building technology companies. He started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a publicly traded EDA software company. Subsequently, he served as President/CEO of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California. Born in Prague, Czech Republic, he holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business. Charlie, his wife Lydia, reside in Los Altos Hills, California.
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