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Dr. Kees Goossens, Eindhoven University of Technology, Netherlands


Better than worst-case design for real-time streaming applications


Traditionally hardware systems are designed using worst-case margins. This becomes more expensive (in area, power) with increasing process variation (within-die, die-to-die). We propose to reduce process margins, reducing traditional manufacturing yield, but at the same time using freedom at the application level to offset this variation. As a result, the number of dies that are guaranteed to be able to execute a real-time application, is improved.


Kees Goossens has BSc in computer science from the University of Wales (1988), and a PhD from the University of Edinburgh (1993). In his thesis he investigated the formal verification of hardware, in particular by using semi-automated proof systems in conjunction with formal semantics of hardware description languages such as ELLA and VHDL. He continued this work at several other universities before joining Philips Research in the Netherlands in 1995. At Philips he worked on behavioural synthesis for high-throughput video processing, then on on-chip communication protocols and memory management. Until 2010, at Philips/NXP Semiconductors Research he led the team that defined the Aethereal network on chip for consumer electronics, where real-time performance and low cost are major constraints. He was also part-time full professor at the Delft university of technology from 2007 to 2010, and is currently full professor at the Eindhoven university of technology, where his research focusses on composable (virtualised), predictable (real-time), low-power embedded systems. He is editorial board member for the ACM Transactions on Design Automation of Electronic Systems (TODAES), associate editor for the Springer Journal of Design Automation of Embedded Systems (DAEM), and member of the editorial review board of the Resources Management Association (IRMA) International Journal of Embedded and Real-Time Communication Systems (IJECRTS), and guest editor for several special issues on networks on chip. He is author on 16 patent, and published three books, 150+ articles, with four paper awards (including CODES+ISSS), and his 2003 paper was selected as one of the 30 most influential papers of 10 years of the DATE conference. He is or was steering committee member of ACSD, DATE, NOCS, MPSOC, and TPC member of CODES+ISSS, DATE, DSD, FPL, ICPP, INA-OCMC, PARMA, OMHI, ReConFig, SAMOS, SDR, SOC, VLSI-SOC, and other conferences.

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