14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Dr. Kees Vissers, Xilinx, USA
Novel 10Gbps memcached implementations designed with High Level Synthesis in FPGAs
Current web infrastructure relies increasingly on distributed in-memory key-value stores such as memcached to alleviate scalability issues on existing databases. Typical x86-based systems yield limited performance scalability with average throughput well below 10Gbps. In the presentation we will show a novel dataflow architecture for a complete implementation of the memcached protocol at 10Gbps full line rate, all designed with High-Level Synthesis in FPGA. This implementation outperforms all existing x86 based implementations, and in particular for small key-value pair is 6-10x faster than top of the line multicore x86 implementation We will show measured results with a high-performance network tester and actual hardware for typical workloads as published by Facebook, Wikipedia, Twitter and Flickr. We will explain the speed benefit compared to x86 implementations and will address novel ideas to allow very high storage capacity for these dataflow architectures.
Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research in Eindhoven, the Netherlands, for many years. The work included Digital Video system design, HW-SW co-design, VLIW processor design and dedicated video processors. He was a visiting industrial fellow at Carnegie Mellon University, where he worked on early High Level Synthesis tools. He was a visiting industrial fellow at UC Berkeley where he worked on several models of computation and dataflow computing. He was a director of architecture at Trimedia, and CTO at Chameleon Systems. Today he is heading a team of researchers at Xilinx. The research topics include next generation programming environments for processors and FPGA fabric, high-performance video systems, wireless applications and new datacenter applications. He has been instrumental in the architecture of Zynq and the High-Level Synthesis technology. He is continuously driving new programming environments with novel applications.
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