14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Prof. Keiji Kimura, Waseda University, Japan
A Latency Reduction Technique for Network Intrusion Detection System on Multicores
Network security threats have become a serious problem along with the usage of Internet. An Intrusion Detection System (IDS) detects the attacks to the network by inspecting the packets according to the predefined rules, or signatures. Packet level parallelism is widely used for IDSs on multicores while the latency for processing one packet is still same due to the difficulty of exploiting parallelism from packet matching process. This talk proposes a latency reduction technique of an IDS. The basic idea of the proposed technique is scheduling packet matching signatures as tasks onto cores considering their processing costs. The preliminary evaluations show the speedup of the latency on an Intel Xeon processor by paralellized Suricata, which is one of popular open-source IDSs.
Keiji Kimura received the B.S., M.S. and Ph. D degrees in electrical engineering from Waseda University, in 1996, 1998, 2001 respectively. He was an assistant professor in 2004, associate professor of Department of Computer Science in 2005, and professor in 2012 at Waseda University. His research interest includes microprocessor architecture, multiprocessor architecture, multicore processor architecture, and there compiler. He is a member of IPSJ, ACM and IEEE. He has served on program committee of conferences such as ICCD, ICPP, LCPC, IISWC and ICS.
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