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Prof. Kiyoung Choi, Seoul National University, Korea


Low Energy STT-RAM Cache with Dead Write Prediction


Spin-Transfer Torque RAM (STT-RAM) has been considered as a promising candidate for on-chip last-level caches, replacing SRAM for better energy efficiency, smaller die footprint, and scalability. However, it also introduces several new challenges into last-level cache designs, which need to be overcome for feasible deployment of STT-RAM caches. Among other things, mitigating the impact of slow and energy-hungry write operations is of utmost importance. This talk is about devising a new mechanism to reduce write activities of STT-RAM last-level caches. It is based on the observation that a significant amount of data written into last-level caches is not actually re-referenced again during the lifetime of the corresponding cache blocks. Such write operations, which we call dead writes, can bypass the cache without incurring extra misses. We propose Dead Write Prediction Assisted STT-RAM Cache Architecture (DASCA), which predicts and bypasses dead writes caused by dead-on-arrival fills, dead-value fills, and closing writes. Evaluations show a significant energy reduction (68%) in last-level caches compared to the STT-RAM baseline. It also reduces energy in main memory (10%) and even improves system performance (6% on average). It works for multi-core systems as well as single-core systems.


Kiyoung Choi is a professor of Electrical and Computer Engineering at Seoul National University. He received B.S. degree in electronics engineering from Seoul National University in 1978, M.S. degree in electrical and electronics engineering from KAIST in 1980, and Ph.D. degree in electrical engineering from Stanford University in 1989. He worked for Cadence Design Systems from 1989 to 1991. His research interests are in computer architecture, embedded systems design, low power design, and design automation.

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