14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Prof. Koji Inoue, Kyushu University, Japan
CPU-Memory Power Shifting on High Performance Computing
Power wall is one of the most serious issues for post peta-scale high-performance computing. A promising solution to tackle with this problem is to overprovision hardware components and control the total system power consumption by software, i.e. power capping. In such overprovisioned systems, the key is to translate the limited power budget into sustained performance effectively. This talk introduces a technique of power shifting between microprocessor and memory devices for such purpose. Based on the characteristics of application programs, we attempt to assign appropriate amount of power budget to each hardware components. Our real machine based experiments show that CPU-memory power budget optimization has a great impact on system performance.*
Koji Inoue was born in Fukuoka, Japan in 1971. He received the B.E. and M.E. degrees in computer science from Kyushu Institute of Technology, Japan in 1994 and 1996, respectively. He received the Ph.D. degree in Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University, Japan in 2001. In 1999, he joined Halo LSI Design & Technology, Inc., NY, as a circuit designer. He is currently an associate professor of the Department of Advanced Information Technology, Kyushu University. His research interests power-aware computing, high-performance computing, dependable processor architecture, secure computer systems, 3D microprocessor architectures, and multi/many-core architectures.
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