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Dr. Marcello Coppola, STMicroelectronics, France


Low power multicore architecture using FDSOI technology


In recent years, the number of general purpose processors and hardware accelerator cores in a MPSoC has increased enormously and heterogeneous architectures are becoming commonplace in many application domains. Although heterogeneous architectures can decline in different instances, the main target for all instances is Energy Efficiency. Network-on-Chips (NoCs) are providing the necessary connectivity among different cores and recently gained widespread use as the de-facto standard on-chip interconnection technology for MPSoC. This presentation outlines how a new generation of NoCs that are aware of the underline silicon technology are required in order to reduce power consumption while maintaining the Application constraints. However, maintaining these constraints in a complex NoC that is silicon technology aware is an interesting problem. FD-SOI is a planar semiconductor technology offering the advantages of fully depleted transistors from the 28nm technology node can be combined with a NoC for reducing power. In this presentation we outline some of the possible gains obtained applying DVFS in the range 1.1V downto 0.6 V to a version of the STNoC platform HDL synthesized in planar CMOS028 FDSOI.


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