14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Prof. Masaaki Kondo, The University of Tokyo, Japan
Evaluating Power-Efficiency for an Embedded Microprocessor with Fine-Grained Power-Gating
Power-performance efficiency is still a primary concern in microprocessor design. One of the sources of power inefficiency for current microprocessors is increasing leakage power consumption. Power-gating is a well known technique to reduce leakage power by switching off the power supply to idle logic blocks. In this talk, we present detailed evaluation of fine-grained run-time power-gating for microprocessors' functional units using a fabricated embedded microprocessor called Geyser-3. We also introduce an architecture and compiler co-operative power-gating scheme which mitigates negative power reduction caused by the energy overhead associated with fine-grained power-gating.
Masaaki Kondo received the B.E. degree in College of Information Sciences and the M.E degree in Doctoral Program in Engineering from University of Tsukuba in 1998 and 2000 respectively, and the Ph.D. degree in Graduate School of Engineering from the University of Tokyo in 2003. He is currently an associate professor in the Graduate School of Information Science and Technology at the University of Tokyo. His research interests include computer architectures, high-performance computing, and dependable computing.
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