Dr, Nakajima Masaitsu, Panasonic, Japan


A Multithreaded Multi-core SoC for 4K2K Smart Screen Applications


A Multi core SoC for coming 4K2K smart screen applications is introduced. This SoC mainly consists of 1) Hardware multithreaded quad core processor IPP3.3, 2) HEVC main 10 4K2K @60p video decoder engine, 3) Real time objects recognition engine, 4) Configurable level 3 shared system cache, 5) Non TSV Hybrid memory system with WideIO1 and DDR3.


Dr. Masaitsu Nakajima joined Matsushita Electric Industrial Co., Ltd., (currently Panasonic Corporation) in 1985. Currently he is a CTO of System LSI Business Division, Panasonic Corporation. He is interested in low power and high performance SoC and processor architecture.

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