14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Prof. Ran Ginosar, Technion Institute of Technology, Israel
Plural: Shared Memory Many Core with Hardware Scheduling
The Plural many-core architecture combines hundreds of small cores, many shared memory banks, a hardware scheduler, and two custom active networks-on-chip: cores-to-memories and cores-to-scheduler. Many-Flow, a de-synchronized PRAM-like task-based non-CSP and non-locking programming model for shared memory enables fine-grain pipelined parallelism. A rad-hard 64-DSP-cores version is implemented in silicon, demonstrating the architecture.
Prof. Ran Ginosar received BSc from the Technion and PhD from Princeton University. He has conducted research at Bell Laboratories, the University of Utah and Intel Research Laboratories in Oregon, USA. He is member of the faculty of EE and CS departments at the Technion, and heads the VLSI Systems Research Center. He has also co-founded several start-up companies in the area of VLSI and parallel processing. His research interests focus on VLSI, asynchronous logic and parallel processing architectures.
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