Mr. Shinobu Fujita, Toshiba, Japan


Advancement of Normally-off Processors (Ultra-low-power Processors) based on ultra-high-speed STT-MRAM.


This paper presents a recent advancement of normally-off processors based on ultra-high-speed STT-MRAM presented for MPSoC 2013, where STT-MRAM is used for last level cache for processors. This paper also presents a novel high-speed power gating system with various low power states suitable for the normally-off processors.


He took PhD of University of Tokyo in 1989. He joined Toshiba in 1989. He has been working for new applications based on nonvolatile memory for over 10 years. Currently, he is a Chief Research Scientist of Toshiba Corporate R&D Center and leading a project for development of STT-MRAM based Normally-off Processors.

* If you wish to modify any information or update your photo, please contact the web chairmpsoc2014@imag.fr