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Prof. Tsuyoshi Isshiki, Tokyo Institute of Technology, Japan


Low Power Multicore SoC Architecture for UWB MAC Processing


This talk addresses the multicore SoC architecture design issues for UWB MAC processing for short-distance high-speed wireless communications. The design process involves porting an initial multitask RTOS-based SW design for single-core SoC into RTOS-less multicore SW/HW design to remove the task switching overhead. Multicore architecture is then enhanced with dedicated interprocessor communication interconnects for efficient task synchronization, and also by switching to area/power efficient cores. The final multicore design achieves 3x speedup and 7x power reduction compared to the initial single-core design.


Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently an Associate Professor at Tokyo Institute of Technology, Dept. of Communications and Integrated Systems. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.

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