Prof. Xiaoyao Liang, Shanghai Jiao Tong University, China


Compiler Assisted Dynamic Register File in GPGPU


The large Register File (RF) in General Purpose Graphic Processing Units (GPGPUs) demands tremendous chip area and energy consumption. For a sustainable growth of the size of RF in future GPGPUs, emerging on-chip memory technologies such as embedded-DRAM (eDRAM) have been proposed to replace the conventional SRAM for higher density and lower leakage but with the possible penalty from the periodic refresh operations. This paper explicitly shows that the refresh penalty can be effectively mitigated by leveraging the uniqueness of GPGPU operations. A compiler assisted refresh rescheduling policy can greatly reduce the refresh overhead for maintaining the correctness of the RF operations. The proposed scheme adequately exploits the features in both architecture and compilation, and delivers comparable performance to the SRAM counterpart. At the same time, the energy savings via the removal of large SRAM leakage well compensate for the additional refresh energy. This study promotes the eDRAM-based RF as a promising alternative that enables larger capacity and better power efficiency for future GPGPUs.


Xiaoyao Liang is a professor and the associate dean in the Department of Computer Science and Engineering at Shanghai Jiao Tong University. His research interests include computer architectures, energy efficient and resilient microprocessor design and GPGPU. Xiaoyao Liang obtained his Ph.D degree from Harvard University. He has ample industry experience working as a senior architect or IC designer at companies like NVIDIA, Intel and IBM.

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