14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Prof. Yoshinori Takeuchi, Osaka University, Japan
A Hierarchical Shared Bus Architecture Design Space Exploration Method
In recent years, a design space exploration problem has been raised with an attempt to reduce time and resources for designing an optimal system-on-a-chip (SoC). State-of-the-art SoCs consist of multiple functions including many processors and many cores. This research proposes a design space exploration method considering a hierarchical bus architectures. The AMBA standard bus is focused as a target. It is because AMBA specification is widely used in many SoC industries as an efficient on-chip interconnect. The proposed method explores the architecture candidates, estimates the execution time and the area of each architecture within a very short time.
Yoshinori Takeuchi is Associate Professor of Graduate School of Information Science and Technology at Osaka University. He received his B.E., M.E. and Dr. Eng. degrees from Tokyo Institute of Technology in 1987, 1989 and 1992, respectively. From 1996, he has been with the Osaka University. He was a visiting scholar in University of California, Irvine from 2006 to 2007. His research interests include System Level Design, VLSI design and VLSI CAD. He is a member of ACM, and Computer, CAS, SSC, and SP Society of IEEE.
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