14th International Forum on Embedded MPSoC and Multicore
July 7-11, 2014, Margaux, France
Slides available here!
Mr. Yuichi Nakamura, NEC Corp., Japan
A scalable connection method beyond processor cores
In this talk, I will present about an Ethernet-based transmission-guaranteed, congestion-controlled network using a simplified multi-path aggregation scheme. This network can connect various computer resources as an extension of computer bus network with large throughput and short latency. For example, it can connect more than 100 GPGPU accelerators to one computer systems. Hardware implementation of this scheme is very simple. In addition, packet-loss detection is rapid. Then, I will present about the world of thousand accelerators computing.
Yuichi Nakamura received his B.E. degree in information engineering and M.E. degree in electrical engineering from the Tokyo Institute of Technology in 1986 and 1988, respectively. He received his PhD. from the Graduate School of Information, Production and Systems, Waseda University, in 2007. He is currently a general manager at Green platform Research Labs., NEC Corp. He is also a guest professor of National Institute of Informatics.
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