Slides available here!


Speaker:

Sorin Cotofana, Delft University of Technology, Netherlands

Title:

Haar-based Interconnect Coding for Energy Effective, Reliable Data Transport

Abstract:

As the atomic/nanoscale size silicon limitations are approached, undesirable variability and stochastic error-prone device operation become prominent. As wires are getting narrower and taller, and the wire pitch smaller, the interconnect parasitics worsen, the inter-wire capacitance increases (and thus the susceptibility to neighboring wires interference) negatively impacting the transmission latency and power consumption (the interconnects dominating figures), as well as the transmitted signals integrity. In view of these considerations, in concert with logic optimization, a multi-criteria (e.g., energy, delay, physical area, reliability) design-time interconnect-centric avenue becomes a critical desideratum for high-performance and/or low power SoCs. In view of this, in this talk, we introduce and evaluate Haar based codec assisted data transport structures, e.g., bus segments, Network on Chip interconnects, able to deal with technology scaling related phenomena (e.g., increased susceptibility to proximity coupling noise and transmission delay variability), targeting energy savings at the expense of a reasonably small area overhead. We also present practical evaluation results for 1mm and 10mm long 8-bit buses (without repeaters) implemented in a 45nm commercial CMOS technology under different random, uncorrelated workload profiles, which indicate that the proposed technique enables substantial energy savings and transmission frequency increase, i.e., prove energy and delay effectiveness of Haar augmented data transport. Finally, we present the augmentation of our proposal with a Single Error Correction and Double Error Detection scheme particularly adapted to its structure, in order to cope with very deep sub-micron noise (e.g., supply voltage variations, electromagnetic interference) induced transmission errors and evaluate it in terms of energy consumption and area.

Bio:

Sorin Dan Cotofana received the MSc degree in Computer Science from "Politehnica" University of Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, Delft, The Netherlands, in 1984 and 1998, respectively. He is currently an Associate Professor with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focussed on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored more than 200 international conference and journal papers and received 12 international conference best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design. He served as Associate Editor for IEEE Transactions on Nanotechnology, IEEE Transactions on Circuits and Systems I, and NanoComnet: Nano Communication Networks. He is currently Senior Editor and Associate Editor in Chief for IEEE Transactions on Nanothechnology, Senior Editorial Board member for IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Steering Committee member for IEEE Transactions Transactions on Multi-Scale Computing Systems, and has been actively involved in the organisation of many international conferences, e.g., ISCAS, NANOARCH, ASAP, DATE. He is a HiPEAC member, a member of IEEE Circuits and System Society (CASS) and IEEE Computer Society, past Chair of the Giga-Nano IEEE CASS Technical Committee, and IEEE Nano Council CASS representative.



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