![](http://mpsoc-forum.org/archive/2024/wp-content/uploads/2020/02/frederic-petrot.jpg)
Frédéric Pétrot
Grenoble University, France
Will 4K pages last forever?
Abstract
The page size used for virtual to physical address translation has globally not changed since the late 60’s: the IBM 360, circa 1964, already had 4 KB pages! This 4KB page size has proven to be incredibly robust given the changes in processor architectures, workloads behavior, memory size, and access patterns. However, with 64-bit registers and 57-bit virtual addresses, we have to ask ourselves whether 4 KB is still the optimal size for modern workloads on modern machines. Inherently, the page size has an influence on (a) the miss rate of the translation lookaside buffer, the cache that contains the recent virtual to physical translations, and (b) the memory reclaimed to the system versus actually used memory. Using empirical evidences, we show that depending on chosen trade-offs, 4K, 16K and 32K pages can be the best choices.
Biography
Frederic Petrot received the PhD degree in Computer Science from Universite Pierre et Marie Curie (Paris VI), Paris, France, in 1994, where has been Assistant Professor in Computer Science until September 2004. He joined TIMA in September 2004, where he holds a professor position at Grenoble Institute of Technology, France. His research interests are in multiprocessor systems on chip architectures, including circuits and software aspects, and CAD tools for the design and evaluation of hardware/software systems. He currently holds the Digital Hardware AI Architectures chair of Grenoble Multidisciplinary Institute in Artificial Intelligence. Frederic Petrot received the PhD degree in Computer Science from Universite Pierre et Marie Curie (Paris VI), Paris, France, in 1994, where has been Assistant Professor in Computer Science until September 2004. He joined TIMA in September 2004, where he holds a professor position at Grenoble Institute of Technology, France. His research interests are in multiprocessor systems on chip architectures, including circuits and software aspects, and CAD tools for the design and evaluation of hardware/software systems. He currently holds the Digital Hardware AI Architectures chair of Grenoble Multidisciplinary Institute in Artificial Intelligence.
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