Tsuyoshi Isshiki

Tokyo Institute of Technology, Japan

RISC-V AI Vision Accelerator Design Methodology on C2RTL System-Level Design Verification Framework

Abstract

In this talk, we introduce our recent works on RISC-V embedded AI Vision accelerator using our C++ based system design framework (C2RTL). Utilizing our C++ RISC-V core model (RV32-IMAFD) with cache/MMU and AXI4 master ports, as well as the entire SoC models including AXI4 bus system and slave peripherals, we have developed 2 AI Vision accelerators (conventional CNN and YOLOv8) embedded within the RISC-V processor pipeline, enabling a fully SW-defined low power AI vision platform. Our YOLOv8 accelerator contains 1152 MAC units, 733 GB/s high-bandwidth on-chip memory for sustaining 1.37 TOPs peak performance under 202.5mW, and 4.76 GB/s DMAC for off-chip data transfer of feature maps and weights.

Biography

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Dept. Information and Communications Engineering. His research interests include multimedia SoC designs and RISC-V SoC design methodologies and tools.

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