Arnaud Grasset

ARM, France

Going beyond Vector Processing with the Scalable Matrix Extension for the Armv9-A Architecture

Abstract

The vector processing unit has become an essential component of modern processors to efficiently support key workloads, such as scientific simulations, computer vision, Machine Learning (ML), and Augmented Reality (AR). To address all these different application domains, the Arm architecture has evolved over time to bring vector processing to the widest range of devices from high-performance processors to low-power processors.
With the Scalable Vector Extensions (SVE) which follows Arm Neon, the AArch64 architecture can address the needs of HPC applications, which are characterized by a high level of data parallelism, thanks to its Vector Length Agnostic (VLA) approach, and the support of wider vector lengths.
Building on the Scalable Vector Extensions (SVE and SVE2), the Scalable Matrix Extension (SME) goes one step further to bring new processing capabilities to the processor. The talk will present how the Scalable Matrix Extension enable an efficient support of matrix operations. In addition, SME with its streaming mode enables the support of different vector lengths in the same system for optimized and efficient implementation of throughput-oriented applications.

Biography

Arnaud Grasset is a principal system architect at Arm, where he works on vector extensions for the Arm AArch64 architecture. He received the M.S. degree in electrical engineering from the Institut National des Sciences Appliquées de Lyon, France, in 2002, and the Ph.D. degree from the Institut National Polytechnique de Grenoble, France, in 2006. Before joining Arm in 2020, he worked at Thales Research & Technology, France, for many years. His interests include vector processing, HW accelerators, dynamically reconfigurable architectures, dependability and fault-tolerant computing, multi-core processors for real-time embedded systems, and system-level design of MPSoCs.