Thales Research & Tech., France
Last results on the CV32A6 soft RISC-V processor core
RISC-V is an open standard instruction set architecture (ISA) invented at the University of Berkeley, California. Unlike most other ISAs, RISC-V is free to use, and many companies and academics offer RISC processors using this instruction set, taking benefits from a large software ecosystem. Facing the risk of an open-source CPU offer fragmentation at low technical maturity, the OpenHW Group aims at designing industrial-grade export-free open-source RISC-V processor cores. In this context, and after having joined RISC-V International to support the specification of secure and dependable open-source processors in 2018, Thales has been an active leading member of the OpenHW Group since 2019. This strengthened the Thales’s commitment to free open-source hardware architectures based on RISC-V processors. Since two years, Thales Research & Technology has been participating in the design of a soft processor core based on the CV32A6 CPU, derived from the Ariane core (renamed CV64A6) created by the PULP team. This presentation will highlight our last software and hardware achievements and demonstrate the maturity of our computing solution for any FPGA.
Nicolas is leading a research group at Thales Research & Technology, France, focusing on embedded artificial intelligence, RISC-V processor design, DNN inference on FPGAs, edge and quantum computing, and parallel software optimisation.
He received a M.Sc and a M.Eng. in Computer Sciences from INSA, Rennes in 2003, and the PhD degree in Electronics from the University of Rennes in 2006 at the CEA LIST. His PhD focused on the design of a heterogeneous multicore architecture using a hardware real-time operating system. At CEA LIST, Nicolas became a project manager of many national and European research projects, a CEA Senior Expert in multiprocessor modelling and design, the leader of several joint labs with industrials and the head of a laboratory on embedded computing. Nicolas focused its research on multi and many-core architectures, virtual prototyping, reliability, and SystemC/TLM simulation. He initiated the development of a large framework for virtual and hybrid prototyping of multicore architectures named SESAM, and led the research on the Scale parallel SystemC kernel to accelerate the simulation of RTL and TLM virtual prototypes. He was also a scholar visitor at Carnegie Mellon University (CMU) in the CALCM laboratory in 2012.
He wrote, as author and co-author, 12 patents and 40+ papers in conferences and journals in the multi and many-core domain. He has also been a reviewer for several international conferences and journals since 2006.
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