For further information, please contact the General chair: Tohru Ishihara
Benoît de Dinechin
MPPA3 Massively Parallel Processor for Intelligent Systems
Intelligent systems such as those embedded into autonomous vehicles need significant computing capabilities under strict electric energy consumption constraints, which can only be provided by massively parallel computers. However, these systems also require real-time and functional safety guarantees that appear incompatible with classic multi-core processor architectures. We expose the fundamental difference between multi-core architectures and many-core architectures, currently mainly represented by GPGPU processors. By using the MPPA3 processor from Kalray as an example, we illustrate how a many-core architecture can be designed to meet the requirements of intelligent systems.
Benoît Dupont de Dinechin is the Chief Technology Officer of Kalray. He is the Kalray VLIW core main architect, and the co-architect of the Multi-Purpose Processing Array (MPPA) processor. Benoît also defined the Kalray software tools roadmap and contributes to its implementation. Before joining Kalray, Benoît was in charge of Research and Development of the STMicroelectronics Software, Tools, Services division, and was promoted to STMicroelectronics Fellow in 2008. Prior to STMicroelectronics, Benoît worked at the Cray Research park (Minnesota, USA), where he developed the software pipeliner of the Cray T3E production compilers. Benoît earned an engineering degree in Radar and Telecommunications from the Ecole Nationale Supérieure de l'Aéronautique et de l'Espace (Toulouse, France), and a doctoral degree in computer systems from the University Pierre et Marie Curie (Paris) under the direction of Prof. P. Feautrier. He completed his post-doctoral studies at the McGill University (Montreal, Canada) at the ACAPS laboratory led by Prof. G. R. Gao. Benoît authored 12 patents in the area of computer architecture, and published over 55 conference papers, journal articles and book chapters in the areas of parallel computing, compiler design and operations research.