For further information, please contact the General chair: Pierre-Emmanuel Gaillardon
K. Charles Janac
Arteris Inc., USA
Interconnect Physical Optimization
With adoption of 16/14nm processes, valid logic architectures can cause difficulty in closing timing during SoC physical implementation. The problem will only get worse in 7nm process SoCs. Interconnect is the major IP involved in timing closure as it contains clear majority of long wires in the SoC. This presentation covers Arteris IP tool/IP technology called PIANO TM which automates interconnect timing closure assistance to accelerate timing closure while enabling optimization of SoC area and latency.
is the Chairman, President and Chief Executive Officer of Arteris IP. Arteris pioneered the market for Network-on- Chip (NoC) interconnect IP and tools for semiconductor on-chip communications. ArterisIP products are designed into semiconductor chips used in the majority of currently shipping smart phones and latest car electronics for driving assistance (ADAS) and autonomous driving. Charlie started his technology career as employee number two of Cadence Design Systems (originally SDA, Inc.), a publicly traded EDA software company. Subsequently, he served as President/CEO of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in- Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California. He holds B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from the Stanford Graduate School of Business.