17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
For further information, please send email to Frédéric Pétrot
Professor at TIMA Lab - Grenoble University, France
Accurate study and optimization of synchronization barriers in a NoC based MPSoC architectureDownload Slides
Synchronization mechanisms have been a critical issue in the race toward the computing units parallelization observed for almost 20 years. They are used to preserve the initial application services even after the parallelization of the software tasks. For instance, in the OpenMP standard, synchronization mechanisms are added during the compilation phase depending on the specific preprocessor directives added by the programmers. But these synchronization mechanisms may slow down the execution if they are not correctly optimized.
By using an emulation platform, we were able to run and to observe exact time slices of large applications on top of a NoC-based manycore architecture. The instrumentation of the emulation platform has allowed extracting, in a non-intrusive way, cycle accurate timing information of the synchronization barriers of the GNU OpenMP library. This study reveals that a non-useful time expensive function was called during the barrier awakening process leading to large waste of time. Hence, we detail the software optimization of this library allowing to save up to 80% of the awakening phase delay for a 16 cores system. Benefiting this optimization requires no specific care from the application programmer's point of view, but a library update.
Pr Frederic Rousseau received the Engineer degree in computer science and electrical engineering from the University of Grenoble in 1991 and a Ph.D. in computer science in 1997 from the University of Evry - France. He has hold an assistant professor position at the University of Grenoble since October 1999 and a professor position since 2007. He is researcher in TIMA lab. His research interest concerns Systems-on-Chip design and architecture, prototyping of hardware/software systems, including reconfigurable systems and high-level synthesis for embedded systems.