For further information, please contact the General chair: Pierre-Emmanuel Gaillardon
The University of Tokyo, Japan
An efficient micro-architecture for cryptographic engine of IoT devices
Large datapath with small control logic is popular approach for efficient processing. However, we must squeeze the datapath of a processor for a small device, and the processor easily loose the efficiency. Montgomery multiplication is one of the most popular processing of the cryptographic engine, and square division is the conventional approach to squeeze the datapath. I will propose a wide-division approach as an efficient micro-architecture, which enhances operating frequency and cost-performance ratio. The small processor with cryptographic engine is one of the key devices of the terminal side of the IoT, and my approach realizes it.
Fumio Arakawa is a designated researcher of Graduate School of Engineering at the University of Tokyo and a designated professor of Graduate School of Informatics at Nagoya University. His research interests include architecture and micro-architecture of low-power and high-performance processors. He has founded a R&D and consulting company, Famer Systems, Inc. to contribute on industries with his R&D experience. Arakawa has a Ph.D. in electrical engineering from the University of Tokyo. He is a program committee co-chair of the Cool Chips conference series, and the chairman of Microprocessor Technical Committee of Japan Electronics and Information Technology Industries Association (JEITA). He is a member of IEEE and IEICE.