17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
For further information, please send email to Frédéric Pétrot
Keio University, Japan
Accelerator Design for Big Data Processing FrameworksDownload Slides
A combination of 1) data processing frameworks consisting of data store, stream and batch processing and 2) machine learning technologies that can handle large volume, large variety, and high velocity data sets is a key enabler for utilizing Big data. To improve the performance of these technologies while reducing their power consumption, we are currently designing FPGA and GPU based accelerators for various data stores (NoSQLs), stream and batch processing frameworks, and some machine learning algorithms. In this talk, we will show FPGA based accelerator with 10GbE interfaces optimized for I/O intensive components such as stream processing, while GPU cluster for compute intensive components such as batch processing.
Hiroki Matsutani received the BA, ME, and PhD degrees from Keio University in 2004, 2006, and 2008, respectively. He is currently an associate professor in the Department of Information and Computer Science, Keio University. From 2009 to 2011, he was a research fellow in the Graduate School of Information Science and Technology, The University of Tokyo, and awarded a Research Fellowship of the Japan Society for the Promotion of Science (JSPS) for Young Scientists (SPD). His research interests include the areas of computer architecture, interconnection networks, and big data processing.