For further information, please contact the General chair: Pierre-Emmanuel Gaillardon
Design and Analysis of Reduced Precision LSTM Networks on FPGA
In this presentation we will introduce a novel LSTM network for Optical Character Recognition. The network is compute intensive and has internal feedback. We will use the Xilinx reduced precision mapping and training tools to build an efficient implementation with reduced precision on several embedded Xilinx Zynq and MPSoC devices. New results for the trade-offs in accuracy with respect to resources and power consumption will be shown in new pareto optimal solutions. We will compare the results with other state of the art and CPU implementations.
This work is the result of a close cooperation with the University of Kaiserslautern.
Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research in Eindhoven, the Netherlands, for many years. The work included Digital Video system design, HW –SW co-design, VLIW processor design and dedicated video processors. He was a visiting industrial fellow at Carnegie Mellon University, where he worked on early High Level Synthesis tools. He was a visiting industrial fellow at UC Berkeley where he worked on several models of computation and dataflow computing. He was a director of architecture at Trimedia, and CTO at Chameleon Systems. He is recognized contributor to the Chapter on VLIW processors in the book: Computer Architecture, 5th edition: A quantitative approach by John L. Hennessy and David A. Patterson He was a Board member of Beecube, which is now part of National Instruments. Today he is a fellow, heading a team of researchers at Xilinx, including a significant part of the Xilinx European Laboratories. The research topics include next generation programming environments for processors and FPGA fabric, high-performance video systems, wireless applications and new datacenter applications and applications of Machine Learning algorithms. He has been instrumental in the architecture of Zynq and MPSoC and the novel programming environments, leveraging High-Level Synthesis technology. He is continuously driving new architectures and programming environments. His current research includes work on Neural Networks and reduced precision Neural Networks.