For further information, please contact the General chair: Tohru Ishihara
An In-memory Computing Accelerator, CMOS Annealing Machine, to Solve Combinatorial Optimization Problems
A new computing architecture, an annealing machine, which is specialized to solve combinatorial optimization problems, is proposed. The annealing machine maps optimization problems to an Ising model and solves the optimization problems by its own convergence property. We proposed a CMOS annealing machine, a CMOS implementation of the annealing machine, which is a type of an in-memory computing. We constructed prototypes of the CMOS annealing machine and confirmed its operation to solve optimization problems. In this talk, the overview of the CMOS annealing machine and related software and application technologies are presented.
Masanao Yamaoka received the B.E., M.E., and ph. D degrees in Electronics and Communication Engineering from Kyoto University, Kyoto, Japan, in 1996, 1998, and 2007 respectively. In 1998, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, where he engaged in the research and development of low-power embedded SRAM and CMOS circuits. Since 2012, he has been engaged in the research of new-paradigm computing using CMOS circuits.