17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
For further information, please send email to Frédéric Pétrot
Professor at Technion-Israel Institute of Technology, Israël
Shared Memory Manycore with Hardware SchedulingDownload Slides
RC64 is now being fabricated at TSMC on 65nm. It integrates 64 DSP cores, 4MByte on-chip shared memory organized in 256 banks, logarithmic network connecting all cores to all memory banks, and a hardware scheduler. High speed links and embedded networking enable easy scaling by employing many RC64 chips. A novel shared memory programming model is employed. There is no need for cache coherency, and correctness of sharing is formally verified at compile time. OS Kernel and multiple applications have been implemented, including DSP and machine learning, showing near-optimal speedup and high performance-to-power ratio. RC64 is designed as rad-hard for use in satellites, and is also applicable to some terrestrial uses. An open research questions asks which architecture is most suitable when we scale the architecture to more advanced technology and many more cores.
Prof. Ran Ginosar received BSc from the Technion and PhD from Princeton University. He has conducted research at Bell Laboratories, the University of Utah and Intel Research Laboratories in Oregon, USA. He is member of the faculty of EE and CS departments at the Technion, and heads the VLSI Systems Research Center. He has also co-founded several start-up companies in the area of VLSI and parallel processing. His research interests focus on VLSI, asynchronous logic and parallel processing architectures.