17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
For further information, please send email to Frédéric Pétrot
Toshiba Corporation, Japan
Efficient Implementations of Deep Neural Network HardwareDownload Slides
Demand for highly energy-efficient hardware for the inference computation of deep neural networks(DNN) is increasing, because DNN technologies have become used for embedded and IoT edge devices within SoCs. In this presentation, we will introduce technologies to realize efficient implementations of DNN hardware. One of technologies is to use logarithmic computation. Logarithmic encoding enables networks to achieve higher classification accuracies than fixed-point at the same resolution and eliminate large digital multipliers. Another technology that we have proposed is the time-domain neural network (TDNN), which employs time-domain analog and digital mixed-signal processing (TDAMS) that uses delay time as the analog signal. TDNN not only exploits energy-efficient analog computing, but also enables fully spatially unrolled architecture by the hardware-efficient feature of TDAMS. The proposed fully spatially unrolled architecture reduces energy-hungry data moving for weight and activations and contributes to significant improvement energy efficiency. The hardware-efficient feature will be strengthened in future when ReRAM stackable on CMOS becomes available. We also propose useful training techniques that mitigate the non-ideal effect of analog circuits and make employing analog computing for the deep neural network practicable. The proof-of-concept chip with cross-coupled memory instead of ReRAM shows unprecedentedly high energy efficiency of 48.2 TSop/s/W.
Takashi Miyamori received the B.S. and M.S. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1985 and 1987, respectively. In 1987, he joined Toshiba Corporation, Kawasaki, Japan, where he was engaged in the research and development of microprocessors. From 1996 to 1998, he was a Visiting Researcher at Stanford University, Stanford, CA, where he researched reconfigurable computer architectures. Since 1997, he has been working on the development of image recognition processors, configurable processor cores, multi and many-core processors, and acceleration technologies for multimedia and computer vision applications. He is currently General Manager of Center for Semiconductor Research & Development in Toshiba Corporation. He served on a technical program committee for high-performance digital design of ISSCC 2009-2011, ASP-DAC 2003-2004 and ASP-DAC 2007-2008.