For further information, please contact the General chair: Pierre-Emmanuel Gaillardon
Tokyo Institute of Technology, Japan
C2RTL SoC Synthesis/Verification Framework for IoT Edge Devices
In this talk, we introduce our recent works on C++-based system design framework (C2RTL) for IoT edge devices including wireless sensor network modeling and RISC-V MPSoC modeling. In our C2RTL framework, C++ model describes not only the processor microarchitecture, but the entire SoC architecture composed of peripherals, busses and memory subsystems, and also serves as the "source" for synthesizable RTL generation of the entire SoC. The SoC C++ model for a single wireless sensor node, equipped with TinyOS (lightweight wireless sensor network OS) and various HW accelerations for enhancing speed and energy efficiency, is integrated into the open-source wireless sensor network simulation framework (TOSSIM, SUNSHINE). Also on RISC-V MPSoC modeling, we show the easiness of porting different instruction-sets and modifying the processor pipeline structure, as well as introducing cache memories which are fully RTL-synthesizable directly from C++ description.
Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Global Scientific Information and Computing Center. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.