17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
For further information, please send email to Frédéric Pétrot
Hong Kong University of Science and Technology, Hong Kong
Exploration of cache coherence for CPU-FPGA heterogeneous system
Nowadays, the power and performance scaling benefits following Moore’s Law are diminishing due to the power wall and the utilization wall. This has led to the increasing popularity of heterogeneous computing systems, which integrate CPUs with hardware accelerators such as GPUs, ASICs or FPGAs. Among the hardware accelerators, FPGA is considered as one of the most promising candidates due to its overall advantages in performance, power and reconfigurability. CPU-FPGA heterogeneous systems like IBM Power 8 and Intel HARP, where parts of an application can be accelerated on FPGA, are gaining increasing interest. However, how to best explore the memory hierarchy of such integrated systems to achieve the best bandwidth efficiency remains a challenging problem. This talk will introduce the simulation platform we have developed to support a fast architectural exploration of the memory hierarchy and the interesting findings we made related to the trade-offs for different architectures.