Keynote:

• Mario Tokoro, Sony, Japan
  On Designing Dependable Systems for Social Infrastructures
  Most of the systems that our daily life relies on, such as automobiles, trains, ships, airplanes and their traffic control systems; medical devices to hospitals; home appliances and home security systems to police and fire departments; electric, gas, and other energy delivery systems, etc., are using computers and networks for their brains and nerves. Nowadays, many such systems are mutually connected and more and more will be in the future and organize social infrastructures. It is crucially important that services are continuously provided even in the case of incidents. Incidents include overloads, failures, attacks, inadequate operations, and so forth. It is also important that incidents never cause domino crush so that the total system becomes fatal malfunction and that a malfunctioning system will be fixed without stopping the total system. Let us call a system which holds these characteristics a dependable system. Difficulties in designing dependable systems lie in that the specification of the total system cannot be given at the time of designing, as network topology and functions will change and new applications and services will be added. Thus, a closed system hypothesis cannot hold and we have to design such a system as an open system. Hence, new concept and approaches are demanded. In this speech, history, definition, and approaches for designing a dependable system will be discussed.

Mini-keynotes:

• Youn-Long Lin, National Tsing Hua University & Global Unichip Corp., Taiwan
  Design Challenge of a Super-HDTV Decoder
  Rapid development of flat-panel display such as LCD makes possible and affordable super high resolution TV way above current full HDTV standard. Moreover, recent trend of video over IP network makes content delivery in any format. Therefore, we expect commercialization of display with QFHD(3842x2160) or even higher resolution at the begining of next decade. To process/decode huge amount of data, massive parallelism and low power technology is necessary. In this talk, we will analyze the feasibility of implementing a QFHD-capable MPSoC.
  
• Jean-Philippe Fassino, STMicroelectronics, France
  Nomadik Multiprocessing Framework, a component-based programming model for MP-SoC
  The main drawback of MP-SoC approach was the complexity inherent to the distribution of algorithms among several processors. We present Nomadik Multiprocessing Framework, a framework which provides a C component-based programming model that hides as much as possible distribution to software developers while making software architecture explicit in order to minimize development costs. The second purpose was to provide a flexible open infrastructure that allows dynamic loading and configuration of software components in order to minimize resource consumptions and allow third party to exploit the whole hardware by adding their own algorithms.
  
• Thierry Collette, Head of Architectures and Design Unit, CEA LIST, France
  New Multi-Core Architecture means New execution and programming models
  Due to the actual limitation of temporal acceleration for the processors, the special acceleration is the only solution in order to increase performance inside a component. Unfortunately, most of the proposed approaches try to manage a Multi-Core architecture (up to 16 processors) into conservative execution and programming models. For instance, we try to execute heavy sequential code on SMP architectures with a very low rate of parallelism, in spite of burden of work done in tools able to extract parallel information inside code written for sequential machines.  Now technology allows the integration of more than 100 processors inside a component, or a “new generation processor”.  So, the old execution and programming models dedicated for the mono processor can't be used for the real multi-core architecture, and new ones must be proposed in adequacy with the new multi-core architectural concepts. The presentation will give some propositions in this direction.
  
• Hiroto Yasuura, Director of System LSI Research Center, Kyushu University, Japan
  Dependability of MPSoC for Applications in Social Information Infrastructure
  Since SoCs are used in various fields of social information infrastructure systems, which are directly related with human lives, properties and privacies. Dependability of SoC including security and reliability is an important research issue of MPSoC. In this talk, several new features of SoC related with dependability are presented.
• Mark Hampton, Certess, France
  Functional Qualification for SOC
  Functional Qualification is the measurement of a functional verification environment's ability to detect potential design bugs by the injection of functional faults into the device under verification and evaluating if the functional verification environment will indicate an erroneous behavior of the device under verification. Functional qualification can be applied to both software testing and hardware verification thus leading to higher confidence in the functionality of SOC. A common metric for measuring the quality of functional verification for both software components and hardware components in a SOC will be proprosed.
• Deepu Talla, System Architect, Texas Instruments, USA
  A reference design for a DaVinci(TM) technology MPSoC targeting digital imaging consumer products
  With rapidly shrinking time-to-market windows and increasing complexity of SoCs for consumer electronic products, it is imperative to provide additional collateral beyond the SoC, documentation, and tools. Reference designs are intended to cover this gap, with a key factor being the ability to offer manufacturers flexibility and differentiation for their product while removing the need for developing basic software, drivers, algorithms, etc. In this talk, we present a bill-of-materials optimized reference design to address digital imaging devices.

In-depth presentations:

• Masaki Gondo, eSOL, Japan
  The need to blend SMP and AMP within a single RTOS
  Recent symmetric multi-core processors such as ARM MPCore offers good scalability as it allows designs to use anywhere from one ARM11 core to four cores. It is highly suitable for general SMP, but is also a good candidate for real-time AMP operation on specific cores. However, to accomplish both AMP and SMP in a single design requires an RTOS that can match this flexibility and scalability in the same manner. For AMP, typically multiple different OS images are used for each processor. SMP on the other hand, requires one OS controlling multiple cores.  Also, to simplify reusing legacy single core software that is not SMP ready, a new model of scalable RTOS is required to deliver the solutions necessary to cope with these varied requirements. This talk will describe both eSOL's blended AMP/SMP RTOS technology and the tightly integrated debug and profiling support for the new generation of multi-processor solutions.
  
• Subhasish Mitra, Departments of Electrical Engineering and Computer Science, Stanford University, USA
  Robust System Design with MPSoCs: Unique Opportunities
  Robust systems are expected to operate correctly in the presence of hardware failures, software malfunctions, malicious attacks and human errors.  This talk focuses on robust system design in the presence of hardware failures.  It is motivated by an imminent paradigm shift in hardware design resulting from the growing problem of hardware failures in advanced process technologies.  The traditional design paradigm (except for high-end mainframes and safety-critical applications) assumes that no gate or interconnect will ever operate incorrectly during the lifetime of a design.  Such a paradigm will be infeasible in future technologies if we want to fully utilize the potential benefits of smaller devices.  One way to break this barrier is to accept the fact that transistors and interconnects will be imperfect, and design failure-aware robust systems.  To adopt this philosophy for most future systems, not only for mainframes, the costs must be extremely small compared to duplication or Triple Modular Redundancy (TMR). The talk will present techniques and tools for designing hierarchical robust systems globally optimized across multiple abstraction layers - circuit, architecture, runtime, and application - without incurring the high cost of expensive redundancy techniques.  Unique opportunities provided by new generations of MPSoCs in designing efficient and cost-effective robust systems will also be discussed.
  
• Maurizio Paganini, CDI Director, STMicroelectronics, HPC - PM Group - AP Division Core Development & Integration, France
  Nomadik - the ultimate mobile multimedia processing platform
  The Ultimate Mobile Multimedia Processing Platform Multimedia Oriented Application Processors are the classical example of complex System On Chip design requiring a high degree of computing power. STMicroelectronics' Nomadik family has embraced from the beginning the philosophy that the sum gives more than the individual resources, that the solution is not in the mussels but in the co-operation, in the network rather than in the node. A family of solutions is today populating Nomadik product family, each generation introducing an increasing level of Embedded Multi Processing that allows ever finer trade-offs between battery lifetime and performance. Despite the sophisticated levels already achieved today, STMicroelectronics is still envisioning several vectors to make Nomadik Multi Processing solutions more effective and powerful.
  
• Jean-René Lèquepeys, Head of ASIC Design Department, LETI/DCIS/SCME, CEA Grenoble, France
  Key Technologies for wireless sensor networks
• Soonhoi Ha, Seoul National University, Rep. of South Korea
  A model-based embedded SW development methodology for MPSoC
  A noble model-based programming environment of embedded software for MPSoC is proposed. By defining a common intermediate code (CIC) that is independent of the architecture, it separates modeling of the software and implementation optimized for target architecture. The proposed methodology has the following features: (1) It allows us to use diverse models for initial specification. (2) It uses different style of programming for task-parallelism and data-parallelism. (3) It provides multi-phase debugging capabilities: at the modeling stage, at the code generation stage, and at the simulation stage. Preliminary experiments confirm the feasibility and validity of the proposed technique.
  
• Kees Vissers, Xilinx, USA
  Building and programming complete MPSoCs in reconfigurable systems
  Modern FPGA designs are essentially a complete heterogeneous multiprocessor system. In this talk we will show what it takes to build a control-processor sub-system, a number of interfaces, a number of application specific processors and  direct control and data-paths. The processor can boot linux, use device discovery mechanisms, load the appropriate device drivers, and load application systems that are programmed in high-level languages. These application systems contain several processor cores, combined with control and data paths. We will demonstrate this for a number of applications: realistic HDTV systems on the XILINX university board environment, high performance signal processing on the UC Berkeley BEE2. We will illustrate the new system that is the focus of the RAMP project. The RAMP research project is an effort of many teams, where the current system architecture is a close cooperation  between UC Berkeley, Microsoft Research, and Xilinx Research.

Keynote:

• Tryggve Fossum, Intel, USA
  Towards a Personal Super computer
  Many of the successes of SOC have been in low end systems where chip level integration has reduced power, cost, and form factor. In the high performance microprocessor space, the SOC concept is just starting to take hold. In this talk we look at some of the considerations for SOC's in the high end. What does it make sense to integrate? Will we have a Personal Supercomputer on our desk? What will it look like? What are the research opportunities in this area? We consider challenges like on-die interconnecst, power management, memory bandwidth, chip interconnects, and control of chip resources. We consider tradeoffs between core designs, both in size and functionality. We look at some challenging applications and the programming environment. We review some recent product developments and research projects.

Mini-keynotes:

• Olivier Franza, Central Technology Development Group, Intel Massachusetts, Inc., USA
  Clock System Design Risks and Opportunities under the MPSoC Paradigm
  
• Norbert Wehn, University of Kaiserslautern, Germany
  Reliability-Aware LDPC Decoder Architecture
  With the continuous downscaling of microelectronic technology, chip reliability becomes a great threat to the design of future complex microelectronic systems. Hence increasing the robustness of chip implementations in terms of tolerating errors becomes mandatory. In this talk we present a reliability-aware LDPC decoder architecture. We exploit application specific fault tolerance combined with modifications on the algorithmic level to increase the reliability of the decoder implementation with a fairly small hardware overhead on architectural level.
  
• Pieter van der Wolf, Principal Scientist, Research, NXP Semiconductors, The Netherlands
  Infrastructures for Modular Integration of MPSoCs
  The current practice of IP-based SoC integration exposes an overwhelming complexity to the SoC integrator, who has to understand the intricacies of H.264 decoding, 3D graphics, WLAN, 2G/3G cellular communications, etc. in order to integrate these functions into a single SoC with an appropriate SoC infrastructure. We propose an hierarchical SoC integration style where functions are pre-integrated into coarse-grain pre-validated subsystems by domain-experts. Each subsystem is then delivered for SoC integration with a ‘data sheet' containing an abstract characterization of the subsystem in terms of functions, interfaces, protocols, communication workload and associated latency constraints for its correct operation. Such data sheets enable the SoC integrator to integrate a set of subsystems in a modular and predictable way with an underlying SoC infrastructure.
• Hannu Tenhunen, Royal Institute of Technology, Sweden
  Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip
  We introduce a novel agent-based reconfiguring concept for futures Network-on-Chip (NoC) systems. The system control is modeled as multi-level agent hierarchy that is able to increase application fault-tolerance and performance with autonomous reactions of agents. The agent technology adds a system level intelligence level to the traditional NoC system design. Communication and reconfiguring data flows are presented as study cases. Principles of reconfiguration of a NoC on faulty environment are demonstrated and simulated. Probability of reconfiguration success is measured with different latency requirements by Monte Carlo simulations. The effect of redundant capacity in functional units was also examined in the simulations.
  
• Yankin Tanurhan, Sr. Director, Applications and IP Solutions, Actel Corporation, USA
  FPGA based Multi Processor Solutions for System Management in the TCA World
  
• Eshel Haritan, CoWare Inc., USA
  Reconstructing MPSOC – Separate Myth from Facts
  MPSOCs are here!  Multi-Processor systems are being designed today by the leading Semiconductor companies. What methodologies, tools and flows are used? Do the tools and methodologies exist and MPSOC is over hyped as a design problem? Is MPSOC the next inflection point in electronic design automation that will drive new methodologies, tools and flows?  The presentation will examine these questions and will try to provide an answer.

In-depth presentations:

• Soo-Ik Chae, Seoul National University, Rep. of South Korea
  A SystemC-based Design Environment for Multimedia SoCs
  System-level decision such as hardware-software partitioning, memory architecture, and synchronization mechanism is crucial in optimizing the performance, area, and power of a system. In the IP-based design methodology, the system designer employs IP components and the designers of each IP already made their own architectural assumtion. Therefore, it is highly likely that these assumptions are not agree with the system-level decision because the IP components were implemented and selected before being integrated. Furthermore, it is almost impossible to make accurate evaluation of the IP components if they is not fully integrated into the system. Initial system-level decisions are often changed during architecture exploration. Consequntly, the system designers often need to reselect or modify the components, if possible, which can be one of the bottlenecks of the system design. My group are developing a SystemC design environment, SoCBase-DE, to alleviate these problems. The SoCBase-DE consists of three major components: a communication-memory-synchronization (CMS) library, a simulation platform, called DEX, and an architecture synthesis tool (AST). In the CMS library we include various channels whose functions are dedicated to communication, memory, and synchronization and we try to capture all design patterns for the communication primitives recurring in implementing multimedia applications. The SoCBase-DE also provides channel architecture templates (CATs) for each channel, which are parameterized implementations with different performance and area characteristics for architecture exploration. The DEX platform is a mixed-level virtual prototyping environment to simulate and evaluate partially refined system models that contain transaction-level, register-transfer-level, and/or software components. The AST is an interactive design automation tool, which helps the designers to explore the architecture space efficiently. In this presentation, I will describe architecture exploration results for a H.264 decoder implemented by using the SoCBase-DE.
  
• Toshihiro Hattori, RENESAS Technology Corp., Japan
  MPSoc Approaches for low-power embedded Soc's
  Multi-processor/multi-core approach is being used in the low-power embedded Soc's. Because the most suitable multi-core approaches are different for the specific systems, Renesas is supporting many kinds of solutions for MP. First, we present a MP approach for SH-Mobile G1/G2, which embedded 3 CPUs in the chip. SH-Mobile G1/G2 integrates existing multi-chip solutions and adapting more than 20 power domains in order to achieve low-leakage in the system operation. Second, we present SH-X3 that is SH-4A multi architecture, which is designed low-power for AMP, SMP and mixed MP approaches. We will show some low-power techniques for MP approaches.
  
• Doris Keitel-Schulz, Qimonda, Germany
  Memory System Solutions and its Influence on System Partitioning
  Today we are experiencing that the difference in yield in pure memories like DRAM and Flash and yield of memories like SRAM in SOCs are increasing. There is a fundamental difference in memory design and production as compared to SOC design and production. In SOCs the minimum design rules tend to be used all over the place, thus creating a variety of critical topologies; in memory design the real dense rules are used only in the array and the direct adjacent circuitry. Technology and prodcution can concentrate on the optimization of a few well defined topologies. In addition the technology variations are slowing down the shrink path for i.e.  SRAM designs for SOCs. As a result the  search for other solutions like die level 3-D integration startes lately to optimize the use of technologies on system level. One typical application in the mobile communication architecture will pe presented to demonstrate the different trends in system partitioning  for memory hungry systems.
  
• Omar Hammami, LEI - UER-EI - ENSTA, France
  Multiobjective Design Space Exploration of MPSOC with Direct Execution
  System level design is NP-complete and therefore fully integrated multiobjective system level design space exploration (DSE) methodologies are essential to guarantee efficiency of future large scale systems. Indeed, each design step in the design flow from system architecture to place and route represents an optimization problem. So far, different tools (computer architecture, design automation) are used to address each problem separately with at best estimation techniques from one level to another. This approach ignore the various and very diverse vertical relations between distinct levels parameters and provides at best local optimization solutions at each step. Due to the large scale of SOC system level design methodologies need to tackle the system design process as a global optimization problem as an NP-complete problem by fully integrating physical design in the design space exploration. We propose  a Multiobjective Design Space Exploration methodology for MPSOC which closes the gap between these associated tools in a fully integrated approach and which exploits large scale FPGA platforms with hardware in the loop evaluation in order to reduce DSE time and improve TTM. Case studies of heterogeneous multiprocessors demonstrate the validity of our approach. We extend this talk with various research directions.
  
• Rolf Ernst, TU Braunschweig, Germany & Marek Jersak, Symtavision , Germany
  Formal analysis and optimization of heterogeneous networks in industrial practice - from networked systems to MpSoC
  Formal analysis and optimization of heterogeneous networks using compositional formal analysis has reached industrial maturity and is now regularly used in automotive design. As an example, the BMW X5 front steering has been designed and certified with the tool, SymTA/S. The tool opens unprecedented features to optimize an automotive system for robustness and extensibility. As a next step, the tool is now applied to MpSoC communication network analysis and optimization. The talk will outline the current industrial use and the extension to include multi-core memory access analysis for MpSoC. An example will be given.
  

Keynote:

• Hiroaki Takada, Nagoya University, Graduate School of Information Science, Japan
  Embedded System and Multi-Processor Technology Trends  in the Automotive Industry
  In a recent luxuary car, as many as 100 computing units are embedded and play important roles to raise the value of the car.  These computing units have diverse requirements and require different technological solutions.  This talk describes the current situation and problems of embedded system in a car and discusses its future trends with focus on multi-processor and in-vehicle network technologies.  Activities by the TOPPERS Project and Center for Embedded Computing Systems of Nagoya Univ. (NCES) are also descrived.

In-depth presentations:

• Takashi Miyamori, Toshiba, Japan
  MPSoC Architecture Trade-offs for Multimedia Applications
• Frédéric Pétrot, TIMA Laboratory, France
  Abstract executable modeling of MPSoC HW/SW interfaces
  At high abstraction level, Multi-Processor System-On-Chip (SoC) designs are specified as an assemblage of IP's which can be Hardware or Software. The refinement and actual implementation of communication between these IP's of very different nature, known as hardware/software interfaces, is seen as a major design bottleneck because of their intrinsic complexity and heterogeneity. In order to perform early design validation, for both Hardware and Software, and architecture level exploration, flexible executable models of these interfaces are needed at different abstraction levels. In this presentation, we introduce a unified modeling approach to describe models of the hardware/software interface, and show how to generate SystemC executable models form these specifications. The proposed formalism, based on the concept of services, gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling and refinement is presented, using a Motion-JPEG decoder as vehicle.

Mini-keynotes:

• Marcello Coppola, STMicroelectronics, France
  An innovative EDA flow for on-chip communication infrastructure
  Customized network-oriented communication architectures have recently become a must to implement SoCs in 45nm and beyond. To this end, the corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC approach for the on-chip communications, this presentation will address the iNoC toolchain applied to STNoC, the Network on-Chip developed by STMicroelecronics. iNoC will address tools from application mapping to platform implementation and architectural debugging.
  
• Frank Schirrmeister, Imperas, Inc., USA
  The Impact of MPSoC Requirements on Software Programming
  Clock speed increases and Instruction Level Parallelism (ILP) have been the traditional improvements for decades enabling faster software on single core hardware. They have come to a screeching halt. Processors have run into the power ceiling limiting further performance increases and ILP has stopped offering additional improvements in most applications. The only possible alternative for the electronics industry to allow continued delivery of product performance improvements is a fundamental switch to parallel hardware running parallel software, a switch to Multi-processor Systems on Chips (MPSoC). In the multi-processor era the new limiting factor for semiconductor providers to get to revenue has become the ability to deliver efficient MPSoC software development environments. Too many companies with promising hardware architectures have seized to exist already because they failed to enable programmers to use their chips efficiently. The key question faced by MPSoC design teams today is how to enable the MPSoC delivery with an efficient software development environment.
• Kees Goossens, SOC Architectures and Infrastructure (SAI) group, Systems and Circuits sector, Research, NXP Semiconductors, The Netherlands
  Debug, Test, and Security Services on Networks on Chip
  Networks on chips are maturing from the hardware architecture point of view. Beyond their basic function of moving data from A to B, NOCs are now being used for different purposes in the system on chip.  In this talk we show how new functions related to test, debug, and security can be implemented by NOCs.
• Wayne Wolf, Princeton University, USA
  Computer Vision and MPSoCs
  Computer vision is a growing market for MPSoCs and the term "embedded computer vision" has gained currency.  We will survey the state-of-the-art in computer vision algorithms.  We will walk through the vision pipeline and the major algorithms in image understanding.  We will conclude by briefly considering the implications of embedded computer vision for MPSoC hardware and software.
• Jan Madsen , Informatics and Mathematical Modelling, Technical University of Denmark
  If Fomal Analysis is the Answer – What was the Question?
  A key challenge of implementing an embedded systems application on a heterogeneous multiprocessor SoC platform is to find the right mapping of the application onto the platform architecture. The right mapping is dependent on the characteristics of the processors and the network connecting them, as well as the application. As many embedded systems are heavily resource constrained and often safty-critical, there is a strong desire to be able to reason about properties of the system. Although the classical approach of simulation may help us in gaining confidence, it will never be able to make guarantees. However, formal models have promises of being able to give such guarantees – but, can we formally model complex MPSoC systems? And if so, what kind of system properties can we expect to be able to formally verify?
• K. Charles Janac, President and Chief Executive Officer, Arteris SA, France
  When is the use of a NoC Most Effective and Why
  The use of an Network on Chip(NoC) as the on-chip interconnect technology can be highly effective above acertain level of chip complexity. As semiconductor manufacturing processes migrate from 90nanometer to 65nm and leading edge 45nm processes, SoC densities increase dramatically, lowering manufacturing cost per device function. However, power and performance do not improve dramatically so the increased density becomes the main economic driver of improved semiconductor economics going forward. As more functions are placed on a chip, leading edge architectures are increasingly subsystem based, requiring parallelism and high data traffic bandwidth in on-chip communications. Increasing use of multiple standards such as USB, UWB, Bluetooth and etc., are also increasing on chip interconnect complexity. At the same time, gross product margins and time to market productivity remain major challenges. The presentation covers applications of NoCs for two different SoC architectures: 1) wireless and 2) multimedia, The presentation also covers the quantitative improvements SoC designers can expect from using an Network on Chip in these types of applications in order to more effectively manage competing product performance and cost requirements.
• Drew Wingard, CTO, Sonics Inc. USA
  High-performance multithreaded memory subsystems for MPSoC’s
  Many MPSoC’s are targeted at high-volume consumer applications whose performance and cost are dominated by external DRAM bandwidth concerns. In such applications, a principal function of the on-chip interconnect and memory subsystem is to exploit the concurrency of the processing and I/O data flows together with the bank-level concurrency available in modern DRAM’s to optimize total throughput while satisfying a wide range of QoS requirements. This presentation discusses the use of multithreaded interconnects and memory schedulers featuring non-blocking flow control to deliver the required memory performance without requiring either multiple ports on the memory scheduler or peak bandwidth matching between the DRAM and any of the initiating cores.

In-depth presentations :

• Heinrich Meyr, RWTH Aachen University, Germany
  Re-configurable ASIPs : Is there any need for these architectures?
  Application-Specific Instruction-set Processors (ASIPs) find increasingly use in mobile devices to meet an optimum trade-off between the conflicting goals of energy efficiency and flexibility (programmability). With ASIPs, flexibility for an application is retained by having it software-programmable and specialization is achieved by special micro-architectural features. Due to its unique blend of flexibility and energy efficiency, ASIPs serve as an important component of modern System-on-Chips (SoCs). With the high-paced, continuous evolution in the domain of wireless communications (software defined, cognitive radio etc) and multimedia applications (high-definition video processing) it is likely that existing SoCs will render suboptimal performance if new algorithms are mapped onto that in future. This will result into complete re-design or major modification of the platform. To amortize the increasing NRE cost for a system design, it is of great economic importance to ensure longer time-in-market. If one further assumes that the applications follow an evolutionary path then a promising approach appears to be to retain a restricted amount of post silicon flexibility. This leads to the concept of reconfigurable ASIPs (rASIPs). In this talk we report on ongoing work in the area of rASIP. We discuss the (complex) design space, tools and methodologies. In particular we discuss the pros and cons of this approach, captured from both the technical as well as the economical perspective.
• Atsuhiro Suga, Fujitsu Laboratories Ltd., Japan
  Automatic thread distribution mechanism suitable for an embedded multicore processor platform
  We propose a multi-core technology which can support to change a number of cores scalablly while minimizing software change effort in case of porting from a single program to multi-cores using existing OS. We will talk about a programming model, its implementation method, operation examples and performance evaluation environment.
• Michael Vinov, Manager, System Verification Technologies group, IBM Research Lab at Haifa, Israel
  Challenges in the verification of high-end Systems on a Chip
  Recent progress in the VLSI technology combined with ever growing requirements to increased complexity and shortened time-to-market bring new challenges to the design and verification methodologies of modern Systems On a Chip. In my talk I'll describe the novel directions and approaches in development of the IBM high-end SoCs.

Mini-keynotes:

• John Goodacre, ARM, UK
  Extending the Cortex ARM version-7 architecture for next generation multicore
  Built using version 6 of the ARM architecture, the ARM11 MPCore provided ARM's first coherent multicore processor.  As multicore is quickly becoming mainstream, we considered software simplifications and performance enhancements in the architecture for the next generation of ARM MPCore technology processors.  This talk will introduce these enhancements, and why we see this architecture setting the foundation for ARM's next-generation  multicore processors while enabling new usage scenarios.
  
• Gert Goossens, CEO, Target Compiler Technologies, Belgium
  Ultra-Low Power?  Think Multi-ASIP SoC!
  MPSoCs are at the eve of a breakthrough, for new feature-rich devices in high-volume markets like wireless telecom and portable multi-media.  With increasing chip densities and an ever growing quest for functionality and battery autonomy, low energy consumption becomes of the essence in MPSoC design.  Drawing from experience in power-sensitive market segments like hearing instruments, we contend that MPSoC architectures must be heterogeneous to meet the ultra-low power requirements.  Each processor core as well as the on-chip communication network must be customised to the application.  This provides for an optimal balance of arithmetic units and both task-level, data-level, and instruction-level parallelism, resulting in lowest energy consumption.  Multi-core SoCs based on application-specific instruction-set processors (ASIPs) thus push the power envelope to the next level.  We will show how multi-ASIP SoC design becomes a reality thanks to a power-aware retargetable tool suite.
  
• Ulrich Ramacher, Infineon Technologies AG, Germany
  Proposal for comparison of SDR baseband solutions
• Rainer Leupers, RWTH Aachen University, Software for Systems on Silicon, Germany
  HySim: Fast Hybrid Processor Simulation for MPSoC Virtual Platforms
  We present HySim, a novel simulation concept for high speed processor simulation in the MPSoC virtual platform context. As classical instruction-set simulation (ISS) technology has been pushed to its limits, new abstract simulation techniques are required to cope with the ever-increasing speed demands of future manycore virtual platforms. HySim is a hybrid simulation framework that permits dynamic toggling between native code execution and ISS. Thereby, it offers the embedded software developer highest simulation speed, while retaining full simulation accuracy where needed.
• Masaharu Imai, Graduate School of Information Science and Technology, Osaka University, Suita, Japan
  A System Level Modeling Method using SystemC for RTOS Centric Embedded Systems
  Real-Time Operating Systems (RTOSes) is essential to execute real-time applications on embedded systems. One of the key issues to perform a HW/SW Codesign process of such systems is how to model RTOSes and application programs at a high level of abstraction. System level modeling method using System Level Design Language (SLDL), such as SystemC, is one of the most promising approaches that provide us with quick and accurate performance estimation of target systems, and conduct the Codesign process by exploring the architecture design space at an early stage of design process. In this presentation, a system level modeling methodology based on the “RTOS System Profile” is introduced. This methodology also proposes the direction to enhance SystemC language toward system level design, by introducing modeling constructs and libraries with well defined semantics to capture the real-time aspects of RTOS behavior and to model SW processes for performance estimation. The RTOS System profile is divided into sections, each of which handles one of the aspects of RTOS simulation modeling. A complete section is also dedicated for exploiting the usage of RTOS simulation models in different fields of embedded system design, including HW/SW co-simulation, performance modeling, and virtual prototyping.
• Ahmed Jerraya, CEA-LETI, France
  An open platform to build MPSoC from Components
  System-on-Chip, SoC. Modern SoC may include one or several CPU subsystems to execute software and sophisticated interconnect in addition to specific hardware subsystems. This is no more an advanced research topic for academia. 90% of SoC designed since the start of the 130nm process, include at least one CPU. Multimedia platforms (e.g. Nomadik and Nexperia) are already multi-processor system on chip (MPSoC) using different kinds of programmable processors (e.g. DSPs and microcontrollers). This trend of building heterogeneous multi-processor SoC will be even accelerated. SoCs will be composed of multiple, possibly highly parallel processors for future applications such as mobile terminals, set top boxes, game processors, video processors, and network processors. It is easy to imagine that the design of a SoC with more than a hundred processors will become a current practice in few years, e.g. with 45nm technology in 2008. Compared with conventional ASIC design, such a multi-processor SoC is a fundamental change in chip design. These chips will include very sophisticated interconnect such as networks-on-chips (NoC). As a result, design methodologies must change their focus to selecting and using subsystems  as basic components rather than the logic modules, such as gates and ALUs, used by the current methods. This presentation will introduce a design methodhology to build systems from components .

In-depth presentations:

• Kazutoshi Wakabayashi, System CAD, System Devices Res. Labs. NEC Corp., Japan
  MPSoC with many Configurable Processors and design environment
  This presentation introduces our MPSoC for mobile phone, Digital AV and its design environment. Our MPSoC includes a few general purpose MPs like ARM or V850, and many configurable processors and some special hardware. The configurable processors and special hardware are both synthesized from behavioral C description with our CWB behavioral synthesizer, and the entire chip simulation model in C++ or SystemC for the MPSoC is automatically generated. We will discuss various merits on such MPSoC and design environment with some real examples. Also, we will introduce our dynamic reconfigurable chip design environment which can add more flexibility to our MPSoC. Finally, we will explain some algorithm becomes too complex for RTL designers and C-based algorithmic design should be used in such area.
  
• Rudy Lauwereins, IMEC, Belgium
  
  Solving the idle power problem of a multi-core software defined radio
  High performant multi-standard software defined radios with data throughputs of several hundreds of Mbits/s rely on multiple powerful cores to obtain the required computational power and flexibility. This high compute power is only needed while demodulating a packet, not during signal tracking and synchronisation. The latter phases account typically for 99% of time for cellular communication and 90% for wireless local area networks. Using the multi-core array for signal tracking and synchronisation requires a much higher power consumption than the sub-5mW idle power of hardwired single standard modems, mainly because of leakage. We present a multi-staged tracking-synchronisation-demodulation approach to overcome this problem. It uses a highly power efficient yet flexible multi-standard synchronisation processor which achieves a 32-bit equivalent power effiency of 200GOPS/W in 90nm technology and can deliver 5GOPS (16-bit operations) peak compute power. This approach allows to build a truly software programmable multi-standard radio with a competitive average idle power consumption of below 3mW.
• Lothar Thiele, Computer Engineering and Communication Networks Lab, Swiss Federal Institute of Technology (ETH) Zuerich, Switzerland
  Modular Performance Analysis of MPSoC
  Embedded computer systems are getting increasingly distributed. This can not only be seen on a small scale, e.g. in terms of MPSoC, but also in terms of embedded systems that are connected via communication networks. New models and methods need to be developed that enable the modular design and analysis of such systems. The talk covers a class of methods which is based on a worst-case/best-case queuing theory on the one hand and an assume/guarantee interface theory on the other. The appriach allows for the consideration of (a) bursty input events and event streams, (b) heterogeneous composition of scheduling methods (EDF, FP, TDMA, WFQ, ...), (c) distributed computation and communication resources, (d) detailed modeling of event stream correlations and resource behavior, and (d) hard worst case bounds. Besides introducing the basic models and methods, some application studies are presented also. It appears that this class of new methods provides a major step towards the modular analysis and design of predictable and efficient MPSoC.
• Mitsuhisa Sato, University of Tsukuba, Japan
  Towards a high performance parallel platform for dependable embedded systems
  In this talk, I will present the concept of our project on high performance parallel platform of multi-core and multiprocessors systems for near-future dependable embedded systems. We are investigating reliable software technologies with redundant resources of multiprocessors and intelligent power management for embedded high-performance parallel applications. And we are designing network links based on PCIExpress/Gen2 and communication facility to provide fault-tolerance and trade-off between power and performance in the communication layer of the embedded parallel system. We plan to develop a parallel embedded multiprocessor prototype system with the new network links to prove our dependable technologies.
• Hiroyuki Tomiyama, Nagoya University, Japan
  RTOS-centric cosimulation of MPSoC
  Due to the continuously growing size and complexity in embedded software, RTOS has become one of the most important components in embedded systems. In order to validate the entire system functionality, therefore, embedded software should be cosimulated with not only hardware but also RTOS, and such cosimulation should be performed from the very early stage of the embedded system design. This talk will describe our ongoing work on hardware/RTOS/software cosimulation for embedded multiprocessor systems.
• Eric Verhulst, Director, OpenLicenseSociety, Belgium
  Formal modeling and a network centric Real-Time Operating System in less than 2K Bytes as a generic base for MP-SoC and Process Oriented Programming
  Systems Engineering (SE) and in particular embedded software engineering suffers from a lack of a unified and rigourous methodology. As such, Open License Society developed a SE methodology around the paradigm of "Interacting Entities". It was found that this approach is generic and allows a straightforward mapping to a wide range of domains. It was also recognised that such an approach can only work if the runtime environment is semantically coherent with it. A project was undertaken to develop such a network-centric real-time operating system environment using formal modeling. It confirmed the benefits of a unified and evolutionary approach. The resulting network centric OpenComRTOS is based on packet switching, can fit in less than 2KBytes and has a number of architectural improvements for safety, security and real-time behaviour normally not found in traditional RTOS. This software based approach pushes the Process Oriented Programming paradigm to its limits and is a solid base for hardware based MP-SoC and distributed processing developments. Future work will focus on adding dynamic properties (www.openlicensesociety.org).

Keynote:

• Allen C. H. Wu, Syntronix, Taiwan
  Business Changes and Challenges in the Competitive Semiconductor Industry
  The IC market revenue growth as well as gross profit margin has been slowed down since 2000. Companies are facing severe competition in a very crowded market under soaring fab and R&D costs. The cost and time-to-market are the key factors to win this brutal competition and only the strongest player can survive. In order to stay in the ball game, many companies are in the midst of fundamental change. In this talk, we will present the recent business changes and challenges in the IC industry.

Mini-keynotes:

• Joachim Kunkel, Synopsys, USA
  Will MPSoCs make the adoption of ESL tools finally mandatory?
  Many have long been forecasting a large Electronic System-Level (ESL) design automation tools market. So far this market has not materialized and the questions on many people’s mind are "Why?" and "Will it ever?". This talk will try to analize whether MPSoCs represent the design challenge that will finally make he adoption of an ESL methodology and ESL tools mandatory.
  
• Chris Rowen, Tensilica, USA
  Putting MPSOC to Work in Multimedia
  The MPSOC community has been working for a decade on new methods and components, promising to reduce design effort, cost and power, and increase performance, functionality and flexibility.  These goals are particularly highly valued in the rapidly growing domain of multimedia platforms.  In this talk, we look at the pervasive requirements of multimedia SOC designs, and look at how MPSOC methods work - or don't work - in delivering on those promises.  We look closely at energy efficiency, verification, programmability, MP communications, and how new tools, processor building blocks and integration flows have led to rapid changes in high-volume chips supporting audio, video, imaging and wireless media transport.
  
• Masao Nakaya, Executive General Manager of Product Technology Unit, Renesas, Japan
  Economics and Performance of Advanced SoC
  Improvements of economics and performance of SoC have been achieved by a down scaling of the minimum feature size achievable and an up scaling of the maximum chip size. However, miniaturization and high integration cause an increase of expenses for advanced SoC products in recent years. The percentage of design cost has increased compared to total cost, making it necessary to decrease this cost while increasing production/sales quantity. This talk shows current issues and directions of advanced SoC.