David Atienza, EPFL, Switzerland


Thermal Balancing for 3D MPSoCs Using Channel Modulation


While possessing the potential to replace conventional air-cooled heat sinks, inter-tier microchannel liquid cooling for 3D MPSoCs also creates the problem of increased thermal gradients from the fluid inlet to outlet ports. These cooling-induced thermal gradients can be high enough to create undesirable stress in the ICs, undermining the structural reliability and lifetimes of 3D MPSoCs. In this mini-keynote, I describe a novel low-cost design-time solution to compensate the thermal gradient problem in liquid-cooled 3D MPSoC architectures. The proposed method is based on channel width modulation and provides the designers with an additional dimension in the design-space exploration. I will show that setting the channel width modulation can be cast as an optimal control design problem to minimize the temperature gradients in the 3D IC while meeting the design constraints. The proposed thermal balancing technique uses an analytical model for forced convective heat transfer in microchannels, and has been applied to two multi-tier 3D MPSoC designs. The results show that the proposed approach can reduce thermal gradients by more than 40%, while maintaining pressure drops in the microchannels well below their safe limits of operation.


David Atienza received his MSc and PhD degrees in Computer Science and Engineering from Complutense University of Madrid (UCM), Spain, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. Currently, he is Professor of EE and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland, and Adjunct Professor at the Computer Architecture and Automation Department of UCM. His research interests focus on system-level design methodologies for low-power embedded systems and high-performance Systems-on-Chip (SoC), including new thermal-aware design for 2D and 3D Multi-Processor SoCs, design methods and architectures for wireless body sensor networks, dynamic memory management and memory hierarchy optimizations, as well as novel architectures for logic and Network-on-Chip (NoC) interconnects. In these fields, he is co-author of more than 180 publications in prestigious journals and international conferences, several book chapters and three U.S. patents. He has received a Best Paper Award at the IEEE/IFIP VLSI-SoC 2009 Conference, and three Best Paper Award Nominations at the WEHA-HPCS 2010, ICCAD 2006 and DAC 2004 conferences. He is an Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design) and Elsevier Integration: The VLSI Journal. He is also an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008 and member of the Board of Governors of IEEE Circuits and Systems Society (CASS) since 2010.

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