Edith Beigne, CEA-LETI, France




The objective of the talk is to give an overview of high energetic efficiency background, issues and solutions. Nowadays, main trends in complex MPSoC in order to improve the global circuit performances can be resumed to 'high energetic efficiency'. Power management is performed with two main objectives: reduce the global power and increase the global energetic efficiency. The term 'performance' does not anymore only mean high frequency but also low power. It is obvious that when we reduce the global power, we increase the delays and the HP (High Performance)/LP (Low Power) trade-off is extremely difficult to reach. It becomes thus mandatory to estimate the global energetic efficiency to ensure that, at a given frequency, the power consumed is minimum. At architectural level, adaptive circuits open the possibility to find an optimum power/frequency point from ultra low power to very high frequency. In addition, FDSOI technology is also offering today great perpectives allowing MPSoC platforms to handle very large operating supply voltage values and, at the same time, operate at the highest energetic efficiency. In the end, MPSOC platforms must be able to deliver short burst of power at very high frequency and overdrive supply voltage and also to operate at a minimum energy level at very low voltage, both with the smallest timing margins whatever the clock frequency and PVT triplet.


Edith Beigne joined CEA-LETI MINATEC in 1998 first working on RFID systems for biomedical applications. She focused then on asynchronous systems and circuits specifically for ultra low power mixed-signal systems and cryptographic circuits. In 2002, she was in charge of an asynchronous Network-on-Chip design dedicated to a complex Telecom SoC, called FAUST. Since 2005, she is in charge of the low power design within the digital laboratory developping fine-grain power control and local voltage and frequency scaling innovative features. Since 2009, her main focus is to manage power and variability issues in advanced technology nodes including standard bulk and FDSOI. She was leading two complex innovative SoC design in 65nm and 32nm technologies for adaptive voltage and frequency scaling architecture based on Globally Asynchronous and Locally Synchronous architectures.

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