Thorsten Groetker, Synopsys , Germany


Time, Speed, and Gradation


Virtual prototypes have become well-accepted tools for numerous HW/SW development tasks. Currently, two modeling styles are predominant. “Loosely-timed” platform models are employed when the focus is on the functionality of a HW/SW system. Here, temporal accuracy is reduced to a minimum, for performance reasons. Substantially slower cycle-based platform models are used when throughput and latency are of main interest. In the age of multi-processor/multi-core SOCs, use models requiring both timing and high simulation performance gain even more importance than before – most notably HW/SW profiling, for performance and power. The talk will present state-of-the-art technologies addressing these needs. Fast, timed models: an oxymoron? Determining the right abstraction and developing efficient modeling techniques is certainly a challenge. Experimental results demonstrate that a solution does exist though.


Thorsten Groetker is a Principal Engineer with the Synopsys System Level Solutions group. He holds a doctorate degree in Electrical Engineering from Aachen University of Technology. Thorsten is a founding member of the OSCI (now ASI) language working group, and subsequently contributed to a number of OSCI activities including TLM2 and CCI. Thorsten co-authored “System Design with SystemC” and “The Developer’s Guide to Debugging”.

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