12th International Forum on Embedded MPSoC and Multicore
July 9-13, 2012, Québec, Canada
Speaker:Charlie Janac, Arteris, USA
Title:Physical Constraint Aware Network on Chip Interconnect(NoC)
The network on chip (NoC) interconnect approach captures multiple wire, topology, SoC services and performance criteria in an interconnect element IP library and a tool set that goes from the earliest architectural analysis to RTL generation. However, how does one know if the interconnect architecture being contemplated will be efficient or even implementable during the physical design phase? This presentation covers how and why physical design constraint awareness should be incorporated into the earliest phases of SoC architecture development and analysis. A comparison of two SoC architecture topologies is presented, showing differences in physical design time, efficiency and ultimately SoC cost.
K. Charles Janac is the Chairman, President and Chief Executive Officer of Arteris Holdings and its subsidiaries. Arteris has pioneered the market for Network on Chip (NoC) interconnect IP and Tools for on-chip communications in System on Chip (SoC) type semiconductors for use in some of the most complex SoCs being built today. Charlie has nearly 30 years of experience building technology companies. He started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a publicly traded company. Subsequently, he served as President/CEO of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California and has worked for Exxon Chemical Company in technical and sales positions. Born in Prague, Czech Republic, he holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business. He holds a patent in polymer film technology. Charlie, his wife Lydia, and their two sons reside in Los Altos Hills, California.
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